Architecture understanding of STM32H757 MCU

[GauravMore]

we started evaluating the controller architecture with respect to our application requirement. We are referring application note AN5557, Reference manual for the suggested MCU.

While referring the documents, we understand that there are 3 Domain in the overall architecture block diagram. Domain 1 is for M7 , Domain 2 for M4 and Domain 3 for BDMA or IPC communication. But there are some queries regarding the memory and flash utilization of both the cores.

1. It consist of 2 MB Flash divided into 2 banks. But in architecture block diagram, it shows in Domain 1 block, it uses AXI bus for M7 core and ART accelerator for M4 core. Is it possible to allocate 1 flash bank to M7 and 1 flash bank for M4 core. Also what would be the interconnection between them in order to access and run the code from flash? Is it like AXI bus for M7 and ART accelerator for M4, in that case will it affect the code execution time between the cores since it uses 32Bit AHB for M4 core and 64 bit AXI bus for M7 core?

1. In Domain 1, there is a dedicated RAM of 512KB is used for running the code for M7? And for M4 288KB RAM (SRAM1 -128KB +SRAM2 -128KB + 32KB -SRAM 3). But if we want to use 256KB only and other 256K to be used by allocating some critical variables in M4 or M7 core then is it possible to use?

1. Domain 3 consists of 64KB RAM, which is used as a IPC memory please confirm? Whether it can is used as a shared memory in case of inter core communication?

1. Is it possible that we can use following configuration in our project

1. M7 core           Flash – 1MB     RAM – 512/ 256 KB
   1. M4 core           Flash – 1MB     RAM – 288 KB

Also the other memories like DTCM-RAM and ITCM-RAM can be accessible by M4 core? since already we have 512KB RAM for M7 core. If not then what is purpose of 192KB RAM?

1. In Domain 3 BDMA is used and is accessible by both the cores (M7 and M4). But then if we use it as a shared memory then how to use basic DMA for SPI, I2C,USART?

1. Regarding the Dual core communication can we use 64KB shared memory as normal memory instead of the methods mentioned in application note AN5557 (Set up communication, Synchronous protocol and Free RTOS IPC module )? Since both the cores are running in different frequency and using 64 bit AXI and 32 bit AHB bus then will affect the execution while accessing the shared memory ?

1. Do we have secondary bootloader to program the dual core device using some application? This is required since we have not found the bootloader for Dual core MCUs of other controllers like LPC series.

Also let me know if there is anything which I misinterpret any functionality of the MCU.

Thanks

Gaurav More

[TDK]

The "System Architecture" figure in the reference manual provides a good understanding into the interconnections.

 

Both cores can access both banks of flash. Where you put your code is up to you, so yes, you can use one bank for the M7 and another for the M4. That's a common configuration.

Similarly, most RAM (at least AXI SRAM, SRAM1-3) can be accessed by both cores. Using memory in the same domain will lead to potential execution gains.

SRAM4 can also be accessed by both cores. You can use it to talk between them if you want.

DTCM-RAM and ITCM-RAM can't be accessed by the M4 core. The purpose of these tightly-coupled memories is that they are much faster than accessing AXI SRAM.

[GauravMore]

Hi,

Thanks for the quick response. I will evaluate the same and with respect to our application and check as per your input.

BR

Gaurav More

[SofLit]

Hello,

This is a matrix (provided in the reference manual RM0399/rev3/Page108) showing the different combination of CM7/CM4 accesses to different memories and slaves on the product: