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ADC only 4Msps?

MSzaj.1
Associate II

Documentation say ADC have max 4Msps, but it refer olways to 60MHz to adc (60MHz * 15 cycle = 4Msps) but manual say ADC max frequency is 170MHz, then 170MHz * 15cycle = 11Msps.

This clock is different from Fadc (aka adc kernel clock)?

https://www.st.com/resource/en/reference_manual/dm00355726-stm32g4-series-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf

Documentation 7.2.11 ADC clock

8 REPLIES 8
Uwe Bonnes
Principal III

Read RM0440 21.4.3 ADC clocks but the interface clock and the clock used for the ADC.

170 MHz is only the interface clock!

MSzaj.1
Associate II

then what is source of adc kernel clock? and what prescaler register it or have some default prescaler (and adc kernel clock is depend on sysclock?)?

MSzaj.1
Associate II

I read RM0440 21.4.3 and I know AHB bus could have different clock that ADC clock, but still 7.2.11 say about ADC clk not AHB bus.

"Alternatively, the ADC clock can be derived from the AHB clock of the ADC bus interface", then it could have same clock that interface?

MSzaj.1
Associate II

if PLL 'P" and SYSCLK is only for source interface clock, then where is source clock for ADC conversion?!

0693W000001s93fQAA.png

You're expected to select a clock and prescalers to have the clock at the mux to be 60 MHz or less.

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S.Ma
Principal

well if the spec gives msps probably there is an analog limit more than digital clocking one. dig the adc electrical spec in datasheet

MSzaj.1
Associate II

Thanks for answer. In https://www.st.com/resource/en/datasheet/stm32g474cb.pdf we have ADC characteristics and there is lmitation. Then there is problem with samples... examples from cube firmware packet have set ADC clock to 170MHz and it work, however it could have different precision and generate EMC issue.

ST should fix their examples to correct ADC clock value.

MSzaj.1
Associate II

Hi all,

I'm back about this problem. There is possibility to clock ADC with 170MHz clock and run over 4Msps (I run it with 8Msps). Of course documentation say I shouldn't do it, but in examples you (I mean ST) provide ADC clk is set to 170MHz!!! and in cubeMX there isn't any warning that say user exceeds ADC clock value!

I just watch Biricha materials and they use soft generated from cubeMX with probably 170MHz ADC clk and all work great...