ADC DMA data order sometimes is wrong STM32F303RBT6

[JMart.13]

I may have seen other posts discussing this topic, but neither of them helped with this. Does the ADC in the buffer we send to the DMA put the data in order? or is some bug in the code?

I'm reading for 3 analog values and sometimes, it works correspondingly.

the microcontroller I'm using is an STM32F303RBT6

Here is the code I developed for it:

periph::ADC::SetChannelSequence(ADC1_SQR1, ADC_CH_1, ADC_SQ1_1);
periph::ADC::SetChannelSequence(ADC1_SQR1, ADC_CH_2, ADC_SQ1_2);
periph::ADC::SetChannelSequence(ADC1_SQR1, ADC_CH_3, ADC_SQ1_3);
periph::ADC::DMA_Init(ADC1, DMA1_Channel1, adc_dma_buffer, DMA_ADC_BUFFER_LENGTH);

the adc_dma_buffer is just an array of uint_16t since the ADC has a 12-bit resolution, DMA_ADC_BUFFER_LENGTH value is 3, to match the buffer array size.

That SetChannelSequence function sets the SQR register for the conversion sequence. It has worked perfectly since I checked the register. Now, this is the DMA_Init function if it could help:

void DMA_Init(ADC_TypeDef * adc, DMA_Channel_TypeDef * dma_ch, std::uint16_t * buffer, std::uint32_t buffer_length){
	adc->CFGR |= ADC_CFGR_CONT; 
	adc->CFGR |= ADC_CFGR_DMAEN | ADC_CFGR_DMACFG;
	adc->SMPR1 |= (7U << 3U) | (7U << 6U); //max sampling rate 
	
			
	dma_ch->CPAR = (std::uint32_t)(&adc->DR); 
	dma_ch->CMAR = (std::uint32_t)(buffer); 
	dma_ch->CNDTR = buffer_length; 	
	dma_ch->CCR |= DMA_CCR_EN;				
			
			
	Enable_regulator(adc); 
	Enable(adc); 
	Calib(adc); 
	Enable(adc); 
			
}

Thanks for any information.

[Imen.D]

Hello @Juan Martín Castillo​,

You should check the ADC registers.

Is the ADC clock enabled?

Imen

[JMart.13]

Hi @Imen DAHMEN​ , yes, I have the clock activated, At least the RCC one.

RCC->AHBENR  |= RCC_AHBENR_ADC12EN;