ADC Conversion time for stm32h750vbt6 ?

[A.Caliskan]

Hello,

I am trying to measure the adc cycle time with the help of an oscilloscope, what is the most precise and correct solution?, I would appreciate if you could help me what method should I follow to measure it.

[A.Caliskan]

my mistake is already split into 32 Mhz 2. I took GPIO into account as you said in my calculations, but there still seems to be an error.

[thundertronics.com]

update: for rev.V at 12bit you can only set ADC clock to 80MHz, which will result in actual clock value of 40MHz. For higher sampling rate use LL_ADC_SAMPLINGTIME_2CYCLES_5 instead of LL_ADC_SAMPLINGTIME_1CYCLE_5

Check if your h750 chip is marked rev V (revision V), then you should should set ADC clock to 128MHz, because newer rev V chips have additional /2 divider inside:

Also, set revision in STM32CubeIDE configurator:

 

[A.Caliskan]

I use rev v. Looking at the reference manual, f adcx2, then fadc/2, nothing really changes here. by frequency

[thundertronics.com]

your 64 MHz will be divided by "/2 block" 64/2=32 MHz

then 32MHz will be divided by LL_ADC_CLOCK_ASYNC_DIV2: 32/2=16 MHz

So resulting clock is 16MHz. It is two unrelated dividers. Note that "/2 block" could not be turned off, that is why in STM32CubeIDE configurator you must always set ADC input clock to twice of required clock value (on newer rev.V chips).

You need get rid of additional divider here:

set it to "Asynchronous clock mode divided by 1" (no division). Then only internal "/2 block" remains active and resulting clock is 32MHz (if ADC peripheral is fed with 64MHz).

Example: on rev.V, if you set ADC clock to 70MHz, 12bit, sampling time 1.5, ASYNC_DIV1 (no division), then sampling rate would be 35*10^6/(1.5+6.5)=4.375 MHz. 35MHz is because of "/2 block" on rev.V. On older rev.Y you directly set ADC clock to 35MHz.

Note text on the image in my previous post, from  AN5312:

On RevV the ADC kernel clock must be twice the frequency needed for the sampling (as an example, if a 25 MHz clock is needed, ADC kernel clock must be set to 50 MHz)

[A.Caliskan]

In the reference manual fadcx2 is in the "block", so the frequency I entered is just async_2.. isn't it supposed to be like this?.

image attected. 

This image RM0433,page 924(stm32h750vb referance manuel),, According to An5312 there is x2

[thundertronics.com]

Frequency you see in STM32Cube configurator is probably PLL output, outside of ADC rectangle on this diagram. Then it divided by some LL_ADC_CLOCK_ASYNC_DIVn and also always divided by "/2". Note that STM32CubeIDE configurator only gives warning if you configure PLL to value greater than 80MHz to feed the ADC. It consistent with reference manual and "/2" interpretation for rev.V (maximum frequency ADC clock around 40MHz, exactly what we get after dividing 80 by 2).

[A.Caliskan]

"It consistent with reference manual and "/2" interpretation for rev.V" okey but its have x2 ,If you look at the picture above( RM0433).so if we want 40 mhz adc, pll should set 40mhz and LL_ADC_CLOCK_ASYNC_1 should be done.

[thundertronics.com]

no, the meaning is that you must provide 2 x adc_ker_ck to ADC to obtain adc_ker_ck. There is no 2x multiplier block there. Also, check AN5312:

On RevV the ADC kernel clock must be twice the frequency needed for the sampling (as an example, if a 25 MHz clock is needed, ADC kernel clock must be set to 50 MHz)

[A.Caliskan]

I get it now, When I set the frequency as you said, it goes up to a maximum of 80 mhz.,,

but datasheet it says it can go up to 100 mhz... Unfortunately, the sampling time is still very slow, even if I do as you say. 

[thundertronics.com]

I've checked several H745 and H750 in LQFP100 package and it works flawlessly for around 40mhz ADC clock (adc input set to 80MHz). I only run into lost samples when used timer for triggering ADC1,2,3 at those frequencies+DAC, and was pointed out that for maximum performance mode timer trigger option should be avoided, and this problem was resolved. Also I've noticed if you overclock it too much, it may either refuse to work or jump to a lower sampling rate and look pretty normal, or show a distorted waveform. You can upload IOC file and any code if you change some timings manually. Why you've mentioned that sampling rate must be 5.68 Msps?

Srate=50*10^6/(2.5+6.5)=5.555556e6= 5.6 [MHz]. I have doubts that stm32h750vbt6 will work well at 50MHz ADC (100MHz input before "/2" divider). I do not remember why, but I stopped by overclocking it just a little bit above 38MHz (76MHz before "/2" on rev.V), and 38MHz is stated in AN5354 for LQFP100. Signal was either distorted or I run into some other problem when tested 50MHz.

Here is some values for 12bit from datasheet and application note AN5354:

From above example Srate=36*10^6/(1.5+6.5)=4.5 Msps

on rev.V provide 72 MHz clock from PLL, Divider=1, Tsampling=1.5, Tsar12bit= 6.5

As you can see, maximum frequency is 38MHz. You can probably use 50MHz.

If you do not need two separate channels, a better alternative is to use ADC1+ADC2 interleaved mode and obtain around 4.5 * 2 = 9 Msps. And maybe overclock it a little bit.

For measurement and debug purposes:

your current DMA buffer size is too small, try to use an array and larger buffer DMA_InitStruct.NbData=1000;

1. enable ADC interrupts
2. start ADC with DMA in circular mode for N samples
3. add void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { with single GPIO toggle here} (LL equivalent of this)

Measure frequency with a scope or frequency meter, multiply it by *2*N

Example DMA buffer size 1000 points, scope shows 1kHz,

ADC sampling frequency 1000*2*1000=2000000=2 Mhz