STM32H753 - ADC Synchronous clock mode

[ASlep.2]

There is an inconsistency in the Reference Manual.

The Reference Manual specifies on page 917 that:

"Option 2) has the advantage of using the system without additional PLL. In addition, when
adc_sclk is twice faster than the adc_hclk clock, the latency between the trigger and the
start of conversion is fixed. This can be useful when the ADC is triggered by a timer and if
the application requires that the ADC is precisely triggered without any uncertainty
(otherwise, an uncertainty of the trigger instant is added by the resynchronizations between
the two clock domains)."

At the same time, on page 1036 it says:

"In synchronous clock mode, when adc_ker_ck = 2 x adc_hclk, there is no jitter in the delay
from a timer trigger to the start of a conversion."

Since adc_ker_ck is not the same as adc_sclk, and in fact will always be at least twice slower than adc_sclk, which of the two statements is the correct one?

[Imen.D]

Hello @ASlep.2 

Thank you for having report this.

Let me check and get back to you with updates.

[Imen.D]

Hello @ASlep.2 ,

After Check, it seems that there is a typo in the RM0433 and RM0399.

So, the sentence :

"In synchronous clock mode, when adc_ker_ck= 2 x adc_hclk, there is no jitter in the delay from a timer trigger to the start of a conversion."

should be replaced by :

"In synchronous clock mode, when adc_sclk = 2 x adc_hclk, there is no jitter in the delay from a timer trigger to the start of a conversion."

An internal ticket number: 214936 is submitted to fix the impacted reference manuals.

Thank you for your contribution and for having reported this.

(PS: Ticket number: 214936 is an internal tracking number and is not accessible or usable by customers).