Posted on March 11, 2013 at 14:13Hi
We figured out some ADC channel miss match on STM32F100C8 device, which we couldn't explane. We use the following test setup:
- ADC1_IN0 (PA0) to ADC1_IN3 (PA3) are used.
- Regular group scan mode with DMA is used.
- VDDA = 3.300V is used as reference.
- All for channel are connected together to a OP buffer as common source.
- ADC cloch 12MHz with 55.5cycle sample time.
We got the following test results:
- ADC channel nois is fine +/- 1LSB.
- ADC1_IN1 is fine +/- 1 LSB compared to measured input voltage.
- All other channels are void -10LSB compared to measured input voltage.
- Changing the order within the regular group sequence had no influence.
- Incresing the sample time to 239.5cycle had no influence.
- Disconnecting ADC1_IN0 had no influence (To avoid voltage glitch related to the errate sheet)
- Reducing the ADC clock to 1.5MHz had no influence.
Thasnk for any help in advance.
Raphael
#adc
