2025-05-14 6:17 AM
Hello,
I'm using STM32G474 to implement 6-step trapezoidal BLDC control and want to achieve full hardware-only commutation, without CPU ISR or software toggling.
MCU: STM32G474
Timer: TIM1 (PSC = 169, ARR = 66 → PWM 15 kHz)
Mode: PWM1, edge-aligned
Outputs:
CH1 → PC0 (HU), CH1N → PA7 (LU)
CH2 → PC1 (HV), CH2N → PB0 (LV)
CH3 → PC2 (HW), CH3N → PB1 (LW)
Low-sides must be ON (not PWM) when active
Hall sensors: PA0 / PA1 / PA2 (currently polled)
Commutation handled 100% by hardware (TIM1 + DMA/EXTI if possible)
No CPU ISR or software to switch outputs during commutation (only supervision allowed)
At each Hall change, TIM1 must autonomously switch active phase pair
MC Workbench forces both high/low-side in PWM, incompatible with 6-step where low-sides must be always ON
MC Workbench requires software-managed commutation
Can I route Hall changes (via EXTI or similar) to trigger TIM1 update/DMA to reconfigure outputs automatically?
Is DMAMUX or other peripheral routing usable to feed TIM1 with pre-configured commutation tables without CPU ISR?
Does HRTIM support such hardware-only 6-step commutation natively (better than TIM1)?
Any ST example or app note for this configuration?
Thanks in advance for your help.
2025-05-14 8:33 AM
Hi FPare.1, currently the 6step MCSDK sensor solution is using SW event coming from general timer connected HALL sensors outputs to set up the new steps. No HW automatic solution has been implemented yet. However, you will find information about this kind of implementation with a direct link between general purpose timer (connected to HALL sensors) and advanced-control timer that manage PWM signals into the Reference manual (chapter 29.3.29 "Interfacing with Hall sensors" of RM0440 "Reference manual STM32G4 series advanced Arm®-based 32-bit MCUs"
Best regards
Fabrice