[STM32F7] Using DMA transfert with TIM1 and TIM8 in PWM generator

[ABITT.1]

Hello,

I search information on the managment of the DMA transfert to the timer.

I use the TIM1 and TIM8 to generate 3 PWM output on each of them. The six output are synchronized.

I want to use the DMA to update the timer value, rated on 28µs.

I don't know if I must select TIM1_CH1/CH3/CH3 on the DMA Resquest or if I must select the TIM1_UP ?

what are the difference between this two possibility ?

thanks in advance.

[ABITT.1]

to say you all, I must use DMA with SPI4 and 5 on RX and TX, DMA with TIM1 and TIM8 (CH1/2/3) and DMA with ADC1 (used in Triple mode with ADC2/3)

[waclawek.jan]

Using Update and CCRx preload is the easiest method with relatively well predictible timing.

You of course can use any of the TIM1 CH1/CH2/CH3 as DMA request, if there's enough time from the selected CC event to the next update; or if you don't use preload, then to the next moment in time when any of the CCRx value becomes important. Don't forget, that it takes time until DMA loads the new values to 3 registers, especially since you load the DMA with a bunch of other tasks. Up-down mode makes things more complicated. Draw a timing diagram, with expected range of values, marking the key moments (when CC event happens, when the next Update happens) and estimate viability of any scheme you chose.

Nowhere is said that there must be a solution to your problem in the form as you've presended it. You will be much better off moving SPIs to those handled by DMA1, for example.

JW

[ABITT.1]

I tried the solution "... by CCMRx.OCxPE. Note, that in center-aligned mode, Update event is generated at both overflow and underflow." using the repetition counter.

it work fine with repetition counter value to 4 !!!!

I don't know why '4' ?

Thanks you waclawek.jan for your support.

[waclawek.jan]

I'm not sure about the exact effect of combination of repetition counter and center-aligned mode...

To discuss this further, read out and post content of TIM and DMA registers and the content of memory buffer from where you pick the CCRx values.

JW

[ABITT.1 · Accepted solution]

Hi,

I believe that I found the solution. The repeat counter masks a number of update event. In a center mode PWM, if I update the CRRx in the first half period, I must set the RCR to 1 to update the duty cyle on the next PWM period. This allow to avoid the shadows register in the middle of the PWM period.

f I update the CRRx in the second half period, I must set the RCR to 0 to update the duty cyle on the next PWM period.