[STM32F7] Using DMA transfert with TIM1 and TIM8 in PWM generator

[ABITT.1]

Hello,

I search information on the managment of the DMA transfert to the timer.

I use the TIM1 and TIM8 to generate 3 PWM output on each of them. The six output are synchronized.

I want to use the DMA to update the timer value, rated on 28µs.

I don't know if I must select TIM1_CH1/CH3/CH3 on the DMA Resquest or if I must select the TIM1_UP ?

what are the difference between this two possibility ?

thanks in advance.

[waclawek.jan]

> I want to use the DMA to update the timer value, rated on 28µs.

What do you mean by "timer value" here?

If you want to update the CCRx values (ie. "pulse length" for PWM), the best option is to set CCRx preload, and use the Update (TIM1_UP) as DMA request. That ensures, that the newly set CCRx values get active simultenously in the next TIM period.

JW

[ABITT.1]

Yes, it's for update the CCRx registers.

What are the effects if I shose the DMARequest 'TIM1_CHA/CH2/CH3' ?

The DMA request will be generated on the OC1/2/3 event ?

The UP request is it for generate the DMA request at the end of the ARR periode ?

[ABITT.1]

'TIM1_CH1/CH2/CH3'...

[ABITT.1]

Is it possible to setup a DMA transfert between memory and CCRx register without using pre-estalished mechanism (as the TIM1_UP request for example).

For example, using DMA memory-to-memory and setup de source address into the memory, and the TIM1_CCR1 register as the destination address, with transfert length to 3 (halfword).

[waclawek.jan]

> What are the effects if I shose the DMARequest 'TIM1_CHA/CH2/CH3' ?

> The DMA request will be generated on the OC1/2/3 event ?

Yes.

> The UP request is it for generate the DMA request at the end of the ARR periode ?

Yes.

> Is it possible [...] using DMA memory-to-memory and setup de source address into the memory, and the TIM1_CCR1 register as the destination address, with transfert length to 3 (halfword).

 Yes, but why would you do it? The effect is almost the same as if you write to those 3 registers from processor by program.

JW

[ABITT.1]

I have conflit on DMA requests, I can't use request TIM1_UP and request SPI5_RX. It seem that there isn't other solution to resolve my hardware needs.

[ABITT.1]

My workaround consist on update the CCRx registers of the TIM1. If I update de CCRx register when the timer is running (the timer is configured for PWM in center-aligned mode), is it that the duty cycle will be updated when the CNT restart a new periode (before start the ramp up) ?

Is it depends on the 'auto-reload preload' state (ARPE bit into the CR1 register) ?

Could you explain me what is the behavior of the TIM1 in this cases:

1. ARPE bit active, I modify the CCR1 register value into the middle of the ramp up of the CNT register

1.a the duty cycle is it modified in live ?

1.b the PWM signal keep it centered ?

2. ARPE bit inactive, I modify the CCR1 register value into the middle of the ramp up of the CNT register (the duty cycle is it modified in live ?)

2.a the duty cycle is it modified in live ?

2.b the PWM signal keep it centered ?

[waclawek.jan]

> I can't use request TIM1_UP and request SPI5_RX

You didn't tell us which STM32F7 are you using, but in 'F767 and 'F745, SPI5Rx is available also in DMA2 Stream3 (as Channel 2).

If that is not viable, you can set TIM1_CH4 to compare at 0 or close to 0 (exact DMA triggering with the up-down counting depends on the particular CR1.CMS setting) and use that as the DMA request/trigger source.

The preload of CCRx registers is *not* governed by CR1.ARPE, but by CCMRx.OCxPE. Note, that in center-aligned mode, Update event is generated at both overflow and underflow.

JW

[ABITT.1]

I use the STM32F746