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What are the timing constraints on BOOT0 and \RESET ?

JCase.1
Associate III

I need to know the timing constraints for bootloading (over UART). How long must \RESET be held low to reset? How long must BOOT0 remain high after \RESET is released? I need this for the STM32L4P5, the STM32F423, and the STM32G031. I apologize in advance, since it is certainly published somewhere, but I couldn't find it.

1 REPLY 1
AScha.3
Chief

so here from ds+rm F303 , cortex M4 core :

reset:

0693W00000Y6psWQAR.pngand boot mode set:

0693W00000Y6psMQAR.png0693W00000Y6psHQAR.png 

  • reset min 20us , to be shure, i would make 10ms and fine.
  • boot is set after 4 sysclks after reset...i would make > 1ms and fine.
  • to be shure, for your different chips, look in the respective manuals (timings might be different)
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