USART_SR, clearing sequence of: IDLE, ORE, NF, FE, PE. A silicon level analysis.

[elKarro]

Applies to: STM32L100xx, STM32L151xx, STM32L152xx, STM32L162xx.

Hi,
in order to write robust drivers, I'm kindly asking a few questions to developers who are into the silicon design. This is the 1st:

ref. RM0038 Reference manual Rev 18, paragraph 27.6.1 Status register (USART_SR) vaguely says that error flag(s):
"It is cleared by a software sequence (a read to the USART_SR register followed by a read to the USART_DR register)."

which of the following describes the real case:

0) "It is cleared by a read to USARTx_DR which happens AFTER a read to USARTx_SR, without any other access in between to the USARTx memory space*."

1) "It is cleared by a read to USARTx_DR which happens AFTER a read to USARTx_SR, without any other access in between to the APBx* linked to the USARTx."

2) ???

(*) see 2.3 Memory map - Table 5. Register boundary addresses

Thank you very much in advance.

[TDK]

> I could rephrase your question as: "why do you think that a read to SR followed by a read to DR will clear the flags?".

That is not a restatement of my question, it's a different question. But the answer is simple: because that's literally what the RM says.

Don't overthink it. Coding is hard enough without hallucinating roadblocks. Cheers.

[STea · Accepted solution]

Hello @elKarro ,

After checking I can confirm that scenario 2 is the right scenario:

2) It is cleared by a read to USARTx_DR which happens AFTER a read to USARTx_SR.

even if other accesses are done in between. it does not matter, and it doesn't matter either if it is done by CPU or DMA.

The state machine of UART needs to detect the sequence as described in RM (a read to the USART_SR register followed by a read to the USART_DR register) things can happen in between and access to the UART address space as well.

BR

[elKarro]

Thank you very much @STea !
Maybe this post clarified that joke you asked me about :- D
Thanks again.

[STea]

Hello @elKarro ,

yep, it's clear as your clearing sequence of: IDLE, ORE, NF, FE, PE . :p

BR