Building discrete power supply for STM32N6

[flexiglass]

I'm following along AN6000 to bypass the internal SMPS of the STM32N6 and use my own SMPS and LDOs power several of the power rails for the MCU and have some questions:

1. In section 3.2 "System power/up/uncontrolled power-down sequence", the document states that the bootloader software must disable the internal SMPS by clearing the SDEN bit in PWR_CR1 register. Is this behavior configurable via CubeMX setting, or needs to be set manually in bootloader and if so, is this achievable once Vdd comes on?

2. In the same section, it states that the PWR_ON signal is activated and Vddcore, Vdda18x and Vddperiph are enabled. The PWR_ON signal is asserted automatically once the power thresholds are reached, correct, or do I have to set the signal manually?

3. In section 2 "Discrete power supply topologies", the diagram shows the LDOs and SMPS for Vddcore, Vdd, Vdda1V8_AON, vdda1v8 and Vddperiph but I do not see an LDO or SMPS for Vddio although I see Vdda1v8 powering some IO blocks. My confusion is that the schematic shows Vddio being powered by LD39020ADTPU33R LDO which outputs 3.3V not 1.8V. So, should Vddio be actually 1.8V or 3.3V?

Thank you!

[RomainR.]

Hello @flexiglass 

Here my answers below:

1. By default, after a reset and the execution of the bootROM, the internal SMPS is enabled.
This is the default content of the PWR_CR1 register bit 2 SDEN SMPS step-down converter enable.
According to AN6000 in section 3.2, you should understand that for an external SMPS (bypass) configuration, bit 2 SDEN of the PWR_CR1 register must be cleared in the FSBL code (which is referred to as Bootloader in the document).
Refer to the example below:
STM32Cube_FW_N6_V1.1.0\Projects\STM32N6570-DK\Templates\Template\FSBL\Src\main.c
in the SystemClock_Config() function, it is the role of the following code: HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) which will change the value of SDEN=0.

2. Refer to RM0486 Rev2, section 13.4.1 System supply startup, VCORE supplied in bypass mode (SMPS off).
The digital output PWR_ON (which is in the VDD domain) once activated will drive the external DCDC component for VDDCore and other supply domains: To have PWR_ON = 1, two conditions are required (see Figure 18. Device startup (VCORE supplied from an external regulator)

• VDD present (3.3V or 1.8V)
• VDDA18ON present (1.8V only)

When these two voltages are present and have crossed the internal POR threshold, then PWR_ON = 1 and can be used to drive external LDO or DCDC chip.

3. In the diagram, the configuration of the VDDIOx is shown (as an example) as the configuration of our STM32N6570-DK. VDD Configured at 3.3V with its own external regulator (SMPS or LDO) VDDA18ON at 1.8V You will notice that these 2 supplies are always present with reference to my response 1.

VDDIO2 and VDDIO3 (XSPI-P1 and XSPI-P2 for external memories) are connected to VDDA1V8.
VDDIO4 and VDDIO5 (SDMMCx) are connected to VDD.

The VDD, VDDIOx power rails can be configured to 3.3 or 1.8V (check Table 22 in DS14791 Rev2)
Let me know if it helps?

Best regards,

Romain