TIMx_RCR function description from STM32F103 to STM32L475 change in manual

[Harish1]

Hi,

I found that TIMx_RCR functionality reversed w.r.t timer counter started from F103 to L475 as per the article. Here, I just want to know whether this bug is in the manual or is it reversed when comparing F103 to L475.

Please find below two screenshots from both manuals.

F103:

 

L475:

[Harish1]

No, I have tested in L475 but it is not working like that.

I have written the odd value to RCR after launching the counter the UEV is occurring on underflow interrupt(when the counter starts up count).

[waclawek.jan]

> I have written the odd value to RCR after launching the counter

Post code.

JW​

[Vincent Onde]

Hi @Community member​,

Sorry for this very late answer.... I agree with you, the statement in the user manual only applies if there is an update of the register. And it's for sure missing in the description, we'll have to change this, also adding some pseudo code to make it clearer.

Just to be sure we're on the same page, here are the software sequences.

When the RCR is written prior to start the counter, we have the update on underflow:

 TIM1->RCR = 1;

 TIM1->EGR = TIM_EGR_UG;

 TIM1->CR1 |= TIM_CR1_CEN;

When the RCR is written after starting the counter, we have the update on overflow:

 TIM1->EGR = TIM_EGR_UG;

 TIM1->CR1 |= TIM_CR1_CEN;

 TIM1->RCR = 1;

I hope this helps,

With my best regards (and thanks for your contributions to the community),

Vincent

[waclawek.jan]

Hi Vincent,

Thanks for chiming in.

I fail to see difference between the two snippets you've posted.

(Also, why do you RMW to EGR?)

Jan

@Vincent Onde​ 

[Vincent Onde]

Hi Jan,

Sorry... I've corrected the snippets (and indeed there's no need to RMW the EGR register).

Thanks and best regards,

Vincent

@Community member​ 

[waclawek.jan]

Hi Vincent,

thanks for the clarification.

Can you please try this sequence:

 TIM1->EGR = TIM_EGR_UG;

// insert delay ensuring that the update indeed happens before the RCR write

// as it's a known issue that the update may take time

// and that may cause additional confusion

 TIM1->RCR = 1;

 TIM1->CR1 |= TIM_CR1_CEN;

In short, IMO, you should remove the section talking about relationship between TIM start and position of updates from the RM entirely.

Jan

@Vincent Onde​ 

[waclawek.jan]

One more thing.

> also adding some pseudo code to make it clearer.

I'm not sure. I personally prefer schematics and diagrams, as code IMO often badly reflects timing-related issues (and indeed timing is one of the crucial problems of microcontroller programming). So, I'd suggest to copy the correct narrative from description of TIMx_RCR register, and add one or several timing diagrams such as those which are throughout the whole TIM chapter before the Repetition counter subchapter, except this time showing the varying content of both TIMx_RCR and the internal RCR_CNT, plus the events around them.

JW

[Vincent Onde]

Hi Jan,

I've tested your sequence, and indeed 1 DMB instruction delay is needed to have the correct result. This is why I prefer to start the counter first to let some time for the update to happen.

Anyway, we'll follow your recommendation and better document this, with diagram and timings. And a snippet on top (even if I understand this is not your preferred way :), some customers do prefer).

Best regards,

Vincent

@Community member​ 

[waclawek.jan]

Thanks, Vincent, for having a look at this and commenting.

Jan

@Vincent Onde​