STM32H7 Ethernet Not Working

[PMart.1]

Hi There,

I am trying to run the ethernet example from the 1.7.0 version of the STM32H7 firmware at STM32Cube_FW_H7_V1.7.0\Projects\NUCLEO-H743ZI\Applications\LwIP\LwIP_HTTP_Server_Netconn_RTOS.

The only modifications I have performed from the provided example code is I have disabled DHCP to use a static IP address (#define LWIP_DHCP 0).

I am trying to run this on the Nucleo-H743ZI2 development board and I cannot get any response to ping. If I attach the debugger, I can see the STM32 is receiving ARP requests and trying to send out ARP responses. Additionally, if I probe the TXD0/TXD1/TXEN lines on the 8742A PHY chip I can see the lines moving periodically in response to ARP queries. Duration looks good, but I have not parsed out the individual bits.

I have tried this on multiple boards, and additionally on a custom STM32H753x board all with the same behavior.

I have also followed all advice here in this page https://community.st.com/s/article/FAQ-Ethernet-not-working-on-STM32H7x3

I have also tried adding the SCB_CleanInvalidateDCache() in the ethernet low_level_output() function.

I have disabled all firewalls and verified I can ping other devices no problem.

I have double checked all SolderBridges and Jumper Wires are set correctly for ethernet based on the Nucleo data sheet.

My questions are:

1. Can someone verify the latest 1.7.0 LwIP_HTTP_Server_Netconn_RTOS example project is functioning on the Nucleo-H743ZI2 dev board? 
2. Does someone have a known working hex file you could provide so that I can verify my hardware is working?

Thank you for any assistance you can provide.

#NUCLEO

#NUCLEO-H743ZI2

#STM32H743ZI

#[STM32 MCUs]​

#STM32H7​

[Manu Abraham]

The next thing that brings to my mind, is that you initially mentioned you played with Dcache cleanup in the code.

Maybe the sample is a bit messed up ? Maybe check with a freshly extracted archive ?

Unlikely hardware issue, that multiple boards behave the same way.

[PMart.1]

Hi rromano001.

• Yep the PHY indicates auto-negotiation is complete with 100BASE-TX full-duplex speed indicated. Register 31 (LAN8742_PHYSCSR) has a value of 0x1058.
• Yep Standard Nucleo board. One difference is the PHY chip says SMSC8742 on it instead of LAN8742?
• Not sure I understand but I can see modulation on RX+/- and TX+/- lines in the ethernet cable.
• Yep I can RXD0 and RXD1 input (and I believe they are working as things seem to be getting into the board no problem)

[PMart.1]

Manu Abraham.

Can you provide more details on the sample bit? Is that something I can check while debugging?

I tried downloading your hex again but it's the exact same.

Thanks again for all your help!

[Manu Abraham]

You can simply add a few printf() in the code, STLink V3 has a Serial port on it. Have a look at what port it is on your system.

Open a terminal app on that serial port. Your printf's would be there.

All you need is a fputc() implementation, for printf to work.

If you need one, this one does it:

/**
 * Simple printf with USART3
 * Debug over ST Link Virtual COM Port
 */
 
#include "stm32h7xx_ll_bus.h"
#include "stm32h7xx_ll_cortex.h"
#include "stm32h7xx_ll_gpio.h"
#include "stm32h7xx_ll_pwr.h"
#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_system.h"
#include "stm32h7xx_ll_usart.h"
#include "stm32h7xx_ll_utils.h"
 
#include "string.h"
#include <stdio.h>
 
struct __FILE {
	int handle;
};
 
FILE __stdout;
FILE __stdin;
 
#define APB_Div			4
 
 
/**
 * System Clock Configuration
 * The system Clock is configured as follow :
 * 	System Clock source	= PLL1 (HSE BYPASS)
 *	SYSCLK(Hz)		= 400000000 (CPU Clock)
 *	HCLK(Hz)		= 200000000 (AXI and AHBs Clock)
 *	AHB Prescaler		= 2
 *	D1 APB3 Prescaler	= 2 (APB3 Clock  100MHz)
 *	D2 APB1 Prescaler	= 2 (APB1 Clock  100MHz)
 *	D2 APB2 Prescaler	= 2 (APB2 Clock  100MHz)
 *	D3 APB4 Prescaler	= 2 (APB4 Clock  100MHz)
 *	HSE Frequency(Hz)	= 8000000
 *	PLL_M			= 4
 *	PLL_N			= 400
 *	PLL_P			= 2
 *	PLL_Q			= 4
 *	PLL_R			= 2
 *	VDD(V)			= 3.3
 *	Flash Latency(WS)	= 4
 */
static void SystemClock_Config(void)
{
	/* Power Configuration */
	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
	while (LL_PWR_IsActiveFlag_VOS() == 0) { }
 
	LL_RCC_HSE_EnableBypass();
	LL_RCC_HSE_Enable();
	while (LL_RCC_HSE_IsReady() != 1) { }
 
	LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
 
	/* Main PLL configuration and activation */
	LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
	LL_RCC_PLL1P_Enable();
	LL_RCC_PLL1Q_Enable();
	LL_RCC_PLL1R_Enable();
	LL_RCC_PLL1FRACN_Disable();
	LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
	LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
	LL_RCC_PLL1_SetM(4);
	LL_RCC_PLL1_SetN(400);
	LL_RCC_PLL1_SetP(2);
	LL_RCC_PLL1_SetQ(4);
	LL_RCC_PLL1_SetR(2);
	LL_RCC_PLL1_Enable();
	while (LL_RCC_PLL1_IsReady() != 1) { }
 
	LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
	LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
	LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);	/* PLL1 as System Clock Source */
	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) { }
 
	SysTick_Config(400000000 / 1000);			/* 1ms Systick */
	SystemCoreClock = 400000000;
}
 
void config_usart(void)
{
	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD);	/* GPIO Clk */
 
	LL_GPIO_SetPinMode(GPIOD, LL_GPIO_PIN_8, LL_GPIO_MODE_ALTERNATE);
	LL_GPIO_SetAFPin_8_15(GPIOD, LL_GPIO_PIN_8, LL_GPIO_AF_7);
	LL_GPIO_SetPinSpeed(GPIOD, LL_GPIO_PIN_8, LL_GPIO_SPEED_FREQ_HIGH);
	LL_GPIO_SetPinOutputType(GPIOD, LL_GPIO_PIN_8, LL_GPIO_OUTPUT_PUSHPULL);
	LL_GPIO_SetPinPull(GPIOD, LL_GPIO_PIN_8, LL_GPIO_PULL_UP);
 
	LL_GPIO_SetPinMode(GPIOD, LL_GPIO_PIN_9, LL_GPIO_MODE_ALTERNATE);
	LL_GPIO_SetAFPin_8_15(GPIOD, LL_GPIO_PIN_9, LL_GPIO_AF_7);
	LL_GPIO_SetPinSpeed(GPIOD, LL_GPIO_PIN_9, LL_GPIO_SPEED_FREQ_HIGH);
	LL_GPIO_SetPinOutputType(GPIOD, LL_GPIO_PIN_9, LL_GPIO_OUTPUT_PUSHPULL);
	LL_GPIO_SetPinPull(GPIOD, LL_GPIO_PIN_9, LL_GPIO_PULL_UP);
 
	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3);	/* USART3 Clk */
	LL_RCC_SetUSARTClockSource(LL_RCC_USART234578_CLKSOURCE_PCLK1);		/* Clk source */
 
	LL_USART_SetTransferDirection(USART3, LL_USART_DIRECTION_TX_RX);
	LL_USART_ConfigCharacter(USART3,
				 LL_USART_DATAWIDTH_8B,
				 LL_USART_PARITY_NONE,
				 LL_USART_STOPBITS_1);
 
	LL_USART_SetBaudRate(USART3,
			     (SystemCoreClock / APB_Div),
			     LL_USART_PRESCALER_DIV1,
			     LL_USART_OVERSAMPLING_16,
			     115200);
 
	LL_USART_Enable(USART3);
 
	while ((!(LL_USART_IsActiveFlag_TEACK(USART3))) ||
	       (!(LL_USART_IsActiveFlag_REACK(USART3)))) { }
}
 
int ferror(FILE *f)
{
	return 0;
}
 
int fputc(int ch, FILE *f)
{
	while (!LL_USART_IsActiveFlag_TXE(USART3)) {};		/* Wait for Tx buffer empty flag */
		if (ch == '\n')
			LL_USART_ClearFlag_TC(USART3);
	LL_USART_TransmitData8(USART3, ch);
	return ch;
}
 
int main(void)
{
	SystemClock_Config();
	config_usart();
	printf("STM32H743 printf test\r\n");
 
	while (1) { }
}

[Manu Abraham]

By sample, I meant sample code. You did mention playing with the DCache functions.

"I have also tried adding the SCB_CleanInvalidateDCache() in the ethernet low_level_output() function."

Maybe the code differs from the original sample code. That's what I did mean.

[PMart.1 · Accepted solution]

@Manu Abraham​ @Community member​ 

Ok major breakthrough! Switched JP5 from 1.8V mode to 3.3V mode and everything started working perfectly on the Nucleo Dev board! I couldn't find anywhere in the NSTM32H7 Nucleo-144 boards user manual indicating you have to do this!

It looks like the PHY chip should be able to handle different logic levels using the VDDIO input but maybe that is not the case?

Thanks again for all the help!

[Manu Abraham]

Glad that you were able to fix the problem!

[PMart.1]

Do you know if there are any settings I need to change in software to be able to support 1.8V operations?

[alister]

For bug-fixes and improvements refer https://community.st.com/s/question/0D50X0000C6eNNSSQ2/bug-fixes-stm32h7-ethernet.

If you use it, please post feedback there.

[rromano001]

Glad me too see you were able apply a cure to problem.

About 1.8V operation, some STM32 part have separate VDDIO Power lines to change from 3.3 to 2.5 or 1.8V to save power.

Not sure this feature also affect ETH PHY interface.

Are you developing for a battery powered device?