STM32G070 Flash CFGBSY flag issue report in generated code.

[MHavl]

Hi, I've found an issue in FLASH_WaitForLastOperation function in code generated for STM32G070. May be it is valid for whole family. It is connected with ECC mechanism.

The isseu is that if CFGBSY of flash SR is set it is never cleard until reset. So if it is set no write to flash is possible.

I found that CFGBSY is set when any write to flash is done. In my case when a write to an uninitialized pointer. Error bits are not set to flash SR register.

Sulution is to do second write to flash. Then CFGBSY is cleared and error bits are set. Error bits is then cleared as usual.

I added followed code to FLASH_WaitForLastOperation after check of BSY1 flag and function is able to recover flash now.

  time_cnt = Timeout;

  while((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U)

  {

   if (time_cnt == 0)

   {

     return 0xFD;

   }

   time_cnt --;

  }

if(FLASH->SR & FLASH_SR_CFGBSY)

  {

   *(uint32_t*)FLASH_BASE = 0xFFFFFFFF;

  }

...

I expected due to datasheet that PGSERR shall be set. (Programming sequence error

Set by hardware when a write access to the Flash memory is performed by the code while PG or FSTPG have not been set previously.)

But it seems that error check is run after second write is done. Flash with ECC expect two consequent writes.

[Legacy member]

Hi MHavl,

The reason why the CFGBSY flag is set, is that you try to program 32bit data.

In Reference Manual you can find:

It is only possible to program a double word (2 x 32-bit data).

• Any attempt to write byte (8 bits) or half-word (16 bits) sets SIZERR flag of the FLASH

status register (FLASH_SR).

• Any attempt to write a double word that is not aligned with a double word address sets

PGAERR flag of the FLASH status register (FLASH_SR).

So FLASH peripheral mechanism waiting for next 32bit, due to the fact that there is no timeout, the flag will never be cleared (unless another 32bit will be programmed, then in FLASH->SR you can find PGAERR).

Best regards

Adrian