High Level Problem Description:
STM32F4xx:
Produced on STM32F427IIHx
What happens:
When SPI as master, full duplex, 8 bit & ~1MHz clock speed and doing longer transmissions (e.g. 10 - 60 bytes) using interrupts the current implementation in Keil::STM32F4xx_DFP V2.14.0 produces RX overrun error.
Why (after investigation):
The TX empty interrupt can fire in succession without RX not empty being flagged. This means there is not time to empty the receive register in time to avoid overrun condition. In other words, the silicon implementation does not guarantee interrupt flags/interrupts will respond in time to avoid overrun condition.
Proposed conceptual fix (verified):
Disable TX empty interrupt after transmit until receiving corresponding data then enable again, unless all data has been received (end of transmission).
STM32H7xx:
Produced on STM32H743BITx
What happens:
When SPI as master, full duplex, 8 bit & ~1MHz clock speed and doing longer transmissions (e.g. 10 - 60 bytes) using interrupts the current implementation in Keil::STM32F4xx_DFP V2.14.0 produces RX overrun error.
Why (after investigation):
The TXP interrupt can fire in succession without RXP or DXP being flagged. This means there is not time to empty the receive register and or FIFO in time to avoid overrun condition. In other words, the silicon implementation does not guarantee interrupt flags/interrupts will respond in time to avoid overrun condition.
In my specific use case sending bytes, when the available FIFO buffer is filled (when hspi->RxXferCount - hspi->TxXferCount > 7) further data transmission often typically/often result in the overrun condition.
Proposed conceptual fix (verified):
Disable TXP interrupt after transmitting to right before the limit of FIFO (configuration dependent) until receiving enough of the corresponding data then enable again, unless all data has been received (end of transmission).
I am happy to provide more specifics/code on the proposed fix once this tickets is looked at and more details are required.
