STM32F4 SPI with DMA, LL API: no interruption at the end of the transfer

[FWX]

Hello,
I am using a STM32F427 to read and write data to EEPROM Serial 256-Kb SPI
CAT25256. I use LL API, and DMA full-duplex over SPI. I manage myself the Chip Slect signal.
I can see with logic analyser that datas are sent and received to/from EEPROM correctly.
But I do not have interruption from DMA, neither input or outputstream.
I do not understand why.
The only way to detect the end of the transfer is to look at the BSY flag LL_SPI_IsActiveFlag_BSY(pSPI_Instance). Could-you help me to find where is the problem?
Thank you for help.
Best regards,
                                                        FWX.
I 

[Saket_Om]

Hello @FWX 

Could you enable the transfer complete interrupt on SPI and check if it is set after the data transfer?

[FWX]

Hi Omar,
Transfer complete interrupt is enable for both input and output streams in ddi_eeprom_init():

// Enable Transfer error interrupt
LL_DMA_EnableIT_TE(pDMA_SPI_Instance, InputStreamNumber);
// Enable Transfer complete interrupt
LL_DMA_EnableIT_TC(pDMA_SPI_Instance, InputStreamNumber);
// Enable Direct Mode error interrupt
LL_DMA_EnableIT_DME(pDMA_SPI_Instance, InputStreamNumber);

// Enable Transfer error interrupt
LL_DMA_EnableIT_TE(pDMA_SPI_Instance, OutputStreamNumber);
// Enable Transfer complete interrupt
LL_DMA_EnableIT_TC(pDMA_SPI_Instance, OutputStreamNumber);
// Enable Direct Mode error interrupt
LL_DMA_EnableIT_DME(pDMA_SPI_Instance, OutputStreamNumber);

NVIC is also well confgured in MX_DMA_init():

/* DMA2_Stream3_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),9, 0));
NVIC_EnableIRQ(DMA2_Stream3_IRQn);
/* DMA2_Stream4_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),9, 0));
NVIC_EnableIRQ(DMA2_Stream4_IRQn);

It is why I do not understand why I do not have interrupt.
Thank you for your answer.

                                   FWX.

[FWX]

Hi Omar,
Sorry, I answered the question wrong.
For output stream (4), when the output transfer is done, when BSY flag is cleared, the HISR register contains 0x30 (DMA_HISR_TCIF4|DMA_HISR_HTIF4): Transfer complete!So, I do not understand why the interrupt handler DMA2_Stream4_IRQHandler() is not called.
Best regards,

                                FWX.

[Saket_Om]

@FWX 

Could you try with this config for interrupts priorities settings: 

  NVIC_SetPriority(DMA2_Stream3_IRQn, 1);
  NVIC_EnableIRQ(DMA2_Stream3_IRQn);
  NVIC_SetPriority(DMA2_Stream4_IRQn, 0);
  NVIC_EnableIRQ(DMA2_Stream4_IRQn);

[FWX]

Hi Omar,
Yes, with this values for NVIC priorities, interrupt handlers are called for input and output stream. Good!

But the value of 0 is not compatible with FreeRTOS interrupt priority.

How can I solve this conflict?

Thank you.

                          FWX.

[Saket_Om]

@FWX 

To address the conflict between the NVIC priority settings and FreeRTOS interrupt priority requirements, you need to ensure that the interrupt priorities are set within the acceptable range defined by FreeRTOS. Specifically, FreeRTOS uses the configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY setting to determine the maximum priority level that can safely call FreeRTOS API functions.

Here are the steps to resolve this conflict:

• Ensure that configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY is defined correctly in your FreeRTOSConfig.h file.

#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5

• Set the NVIC priorities for your interrupts to be within the range allowed by FreeRTOS. For example, if configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, you should set the priorities of your interrupts to be 5 or higher (numerically lower).

NVIC_SetPriority(DMA2_Stream3_IRQn, 5); // Priority 5
NVIC_EnableIRQ(DMA2_Stream3_IRQn);
NVIC_SetPriority(DMA2_Stream4_IRQn, 6); // Priority 6
NVIC_EnableIRQ(DMA2_Stream4_IRQn);

[FWX]

Hi Omar,
With priority values of 5 and 6, I have the same behavior than at the begining: interrupt handler not called.
I have attached my ioc file.
DMA input and output stream are used during initialization process. The FreeRTOS scheduler is not yet started. But if interrupt priority is not compatible with FreeRTOS, an assert in port.c failed.

Perhaps our values for priorities are not good.
It seems the choice is very delicate.

Thank you for yours help.
                                       FWX.

[Saket_Om]

@FWX 

I see you have many peripherals that are configured with interrupt process.

You have a conflict with other interrupt. To debug the issue, you need to test the SPI transfer without other peripheral working on the setup. And then add them one by one. 

The issue can be solved with a good management of interrupts priorities. 

Could you try with interrupts priorities 5 for the two stream 3 and 4 please, this is to avoid conflict with CAN interrupts? 

[FWX]

Hi Omar,

In the main, I have now only initialization of HAL, SystemClock, GPIO, UART8 (for logs), DMA2 and SPI4.
DMA interrupt priority are set to 5 for input and output.
Same behaviour: interrupt handler not called.
It's a mystery to me...
I'll continue to investigate next week.
Thank you for help.
Best regards.
                      FWX.