STM32F0x: RX fifo threshold not set according to data width by LL drivers

[LFisc.1]

Hi, i noticed, that the LL driver does not set the RX fifo threshold levels according to the datasheet:

"

     Rx buffer not empty (RXNE)

     The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:

      • If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or

        equal to 1/4 (8-bit).

      • If FRXTH is cleared, RXNE goes high and stays high until the RXFIFO level is greater

        than or equal to 1/2 (16-bit).

      An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set.

      The RXNE is cleared by hardware automatically when the above conditions are no longer

      true.

"

When receiving in 8bit mode for example, only every 4th received byte triggers an RX interrupt. On an STM32F4x this was set correctly by the LL drivers, so this is probably a bug and should be fixed.

It can be manually set by

LL_SPI_SetRxFIFOThreshold(SPI1, LL_SPI_RX_FIFO_TH_QUARTER);

[waclawek.jan]

On F4, there's no FIFO in the SPI.

LL means Low Level, mostly it's just renamed direct register access. It's not supposed to deliver any more complex setup within one function call. Most peripherals are supposed to be set up by a series of function calls.

JW

[TDK]

There is no such "LL_SPI_SetRxFIFOThreshold" function in the STM32CubeF4 repository.

https://github.com/STMicroelectronics/STM32CubeF4/search?q=LL_SPI_SetRxFIFOThreshold&unscoped_q=LL_SPI_SetRxFIFOThreshold