ok, got EXTI on SCK, you can probably adapt to NSS (HW) pin:
void SPIP_EnableSCK_EXTI(SPIP_t* pSPIP) { // STM32L4R5
// PD1 = SCK
SYSCFG->EXTICR[0] &= ~(0xF<<4);
SYSCFG->EXTICR[0] |= (3<<4);
EXTI->IMR1 |= GPIO_PIN_1; // interrupt enable
EXTI->RTSR1 |= GPIO_PIN_1; // rising sense
EXTI->FTSR1 |= GPIO_PIN_1; // falling sense
// Above is the simplest way to have EXTI on AF pin.
__HAL_GPIO_EXTI_CLEAR_IT(pSPIP->pSCK->Init.Pin);
__HAL_GPIO_EXTI_CLEAR_FLAG(pSPIP->pSCK->Init.Pin);
//EXTI->IMR1 |= (1<<1);
HAL_NVIC_SetPriority(EXTI1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(EXTI1_IRQn);
}
void SPIP_DisableSCK_EXTI(SPIP_t* pSPIP) {
HAL_NVIC_DisableIRQ(EXTI1_IRQn);
}
void EXTI1_IRQHandler(void)
{
/* USER CODE BEGIN EXTI0_IRQn 0 */
/* USER CODE END EXTI0_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
/* USER CODE BEGIN EXTI0_IRQn 1 */
/* USER CODE END EXTI0_IRQn 1 */
}
DMA needs to know the block size going to be transffered:
- You send the information in a previous transaction
- You have a max incoming RAM buffer size and loop through it. The received data contains the valid block size
Of course, if planning to exchange data full duplex MISO and MOSI, there are two directions, two blocks, two sizes sharing the same SCK clock pulses...
One implemented solution if there are only MCU on the SPI bus is to send data at each edge of NSS, rising edge, I send a small "header" which contains the coming next data size and simultaneously, I received the slave intended block size to receive. Then on NSS falling edge, the DMA do a pure block transfer uninterrupted. In this particular case, NSS is SW controlled and MISO/MOSI at slave are dynamically configured from the NSS dual edge EXTI interrupt. All is handled in a ISR based state machine to hide the details and minimize core load.
