2025-05-12 9:04 AM - last edited on 2025-05-12 9:14 AM by Andrew Neil
When using I2C with DMA on an STM32G4, is there a recommended relative ordering of the I2C event, I2C error, and DMA interrupt preemption priorities?
I have not been able to find anything in documentation about this (though I might have missed it). What I have found is the CubeG4 examples (I2C_TwoBoards_ComDMA) where the DMA, I2C event, and I2C error interrupts all have the same preemption priority (0 for all). I've also found another post where ST recommends the following relative preemption priority values: DMA (0) < I2C error (1) < I2C event (2).
Currently we have the following relative preemption priority values: DMA (8) < I2C event (10) < I2C error (11). In our case the event and error are reversed compared to the above linked ST advice, though we don't remember why. I'm debugging WWDG events that we've traced to an I2C event interrupt storm, and one hypothesis is that the internal state of the HAL I2C driver is getting corrupted by e.g. DMA interrupt preempting an already executing I2C error interrupt. Even if it's not the cause of our issue, I figured it was worth checking with ST if the HAL was assuming some particular interrupt priority ordering.
Thanks
2025-05-12 9:28 AM
Hello @mjones37
Please set you interrupt priorities as below:
/*##-4- Configure the NVIC for DMA #########################################*/
/* NVIC configuration for DMA transfer complete interrupt (I2C1_TX) */
HAL_NVIC_SetPriority(I2Cx_DMA_TX_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(I2Cx_DMA_TX_IRQn);
/* NVIC configuration for DMA transfer complete interrupt (I2C1_RX) */
HAL_NVIC_SetPriority(I2Cx_DMA_RX_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(I2Cx_DMA_RX_IRQn);
/* NVIC for I2Cx */
HAL_NVIC_SetPriority(I2Cx_ER_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(I2Cx_ER_IRQn);
HAL_NVIC_SetPriority(I2Cx_EV_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(I2Cx_EV_IRQn);
Please look to the example below for more details: