osDelay vs debug steps

[ranran]

Hello,

The short story:

I observe difference in behavior between osDelay() compared to IAR debugger steps.

Is there anything which can explain why these two behaves differently ?

The long story:

Recently we changes our FPGA from asynchronous to synchroous + wait delay + different timing.

Now we observe some issues when accessing FPGA .

We test it as following:

while(1){
  wr_value++;
  HAL_SRAM_Write_32b(&g_hfpga, FPGA_BANK_ADDR + wr_offset, &wr_value, 1);
  HAL_SRAM_Write_32b(&g_hfpga, FPGA_BANK_ADDR + rd_offset, &rd_value, 1); 
}

Trying to do steps, I see that the rd_value is not always equal to wr_value, and seems to be related to previous values sometimes.

If I only add osDelay between write/read then I always get the correct values:

while(1){
 wr_value++;
 HAL_SRAM_Write_32b(&g_hfpga, FPGA_BANK_ADDR + wr_offset, &wr_value, 1);
 osDelay(125)
HAL_SRAM_Write_32b(&g_hfpga, FPGA_BANK_ADDR + rd_offset, &rd_value, 1);
}

 Is there anything which can explain the change in behavior between osDelay vs doing steps with debugger ?

Thanks

[Pavel A.]

> Is there anything which can explain the change in behavior between osDelay vs doing steps with debugger ?

osDelay may cause task switch, this is pretty heavy and involved procedure.

Also, if your debugger supports RTOS integration, it can do something "clever" and add to the complexity.

-- pa