I2C read and write without stop condition

[VThan.2]

Using the HAL I2C library, is there any way to generate a continuous stream of scl and sda without a stop bit after the chip address acknowledge and data acknowledge. Otherwise I am planning to use a i2C bitbang library any recommendations? The target chip that I am using does not like the marked segment below

[Bob S]

I second @Harvey White​ the rise and specially fall rates on the clock look way too slow. The falling edge should be pretty close to a vertical line. That said, it doesn't look like the slow clock edges overlap changes in SDA.

The voltage level at the address ACK bit is messed up. And you can see how the two little peaks just cross the logic analyzer digital thresholds to give you the two narrow pulses on the digital SDA line. While the "digital" representation shows ACK for the address byte, looking at the analog version I would not be so sure.

Figure out why you aren't getting a good low/high value for the address ACK. What value pull-up resistors do you have on the I2C bus? Are there resistors on your device's eval board AND on your STM32 board? Are you pulling it to 5V or 3.3V?

[Bob S · Accepted solution]

Just saw your OTHER post about 1.1V I2C levels here https://community.st.com/s/question/0D53W00001M8LwmSAF/i2c-operating-voltages

As mentioned in that thread, you need a level shifter. Also, your pull-up resistor value to the 1.1V supply is too large. The actual value depends on your clock speed and bus capacitance. The I2C spec (NXP UM10204) gives equations for this. Ignoring capacitance and allowing for the standard 3mA current when the line is pulled low, 367 ohms to 1.1V would be the highest usable value.

[TDK]

You have bus contention. Multiple pins are trying to drive SDA which is leading to a logic level between 0 and 1. This is most likely a hardware issue.

[TDK]

Or you're using a 3.3V logic level chip with a 1.1V one, which won't work.

[ssipa.1]

useful notes:

• A single message can contain multiple START conditions. The use of this is so-called “repeated START�? is common in I2C.
• STOP condition always denotes the end of the transmission even if it is issued in the middle of the transaction or the middle of a byte.

[VThan.2]

Hello all,

Thank you for the replies and I finally got some updates and was finally able to get back to this. I agree with everyone that the problem was with the level translation. I was able to resolve it. I ended up using a PCA9517 level converter. Worked very well. I also reduced the clock rate to 20kHz and since I was going through bread boards and hook up wires. My outputs were much cleaner. Thank you everyone.