2023-03-09 06:56 AM
I'm trying to receive a packet of 15125 bytes. The packet is correctly fragmented in 11 packets, but of each fragment only the first 902 bytes are correct, the rest are equals to 0.
ETH_RX_BUFFER_SIZE: 1536
MEM_ALIGNMENT: 4
MEM_SIZE: 16360
LWIP_RAM_HEAP_POINTER: 0X30044000
MEMP_NUM_REASSDATA: 5
MEMP_NUM_FRAG_PBUF: 30
PBUF_POOL_SIZE: 32
PBUF_POOL_BUFSIZE: 2500
IP_REASS_MAXAGE: 10
IP_REASS_MAX_PBUFS: 50
TCP_MSS: 1460
ETH_RX_DESC_CNT: 15
ETH_TX_DESC_CNT: 4
.lwip_sec (NOLOAD) : {
. = ABSOLUTE (0X30000000);
*(.RxDescripSection)
. = ABSOLUTE (0X30000620);
*(.TxDescripSection)
. = ABSOLUTE (0X30000800);
*(.RxArraySection)
} > RAM_D2
2023-03-09 07:46 AM
There are a lot of things to take care of. Have you already found these useful pages?
https://community.st.com/s/article/FAQ-Ethernet-not-working-on-STM32H7x3
2023-03-09 08:17 AM
I don't know the H745 SRAM mapping, but are you sure that all that fitting in there where it should?
For the H723..H735 series (which has a different SRAM mapping than the H745) it was mostly important to set the descriptors in SRAM2.
Data and lwIP stuff can be put anywhere except TCM.
I thin the H74x had some limits concerning ETH / AXI RAM, but not sure.
And can you receive smaller packets without error?
2023-03-09 10:57 PM
It seems to me that everything corresponds to what is described in the guide, except for the MPU. I disabled the MPU.
2023-03-09 11:08 PM
This is memories definition:
RAM (xrw) : ORIGIN = 0X24000000, LENGHT = 512K
FLASH (rx) : ORIGIN = 0X08000000, LENGHT = 1024K
DTCRAM (xrw) : ORIGIN = 0X20000000, LENGHT = 128K
RAM_D2 (xrw) : ORIGIN = 0X30000000, LENGHT = 512K
RAM_D3 (xrw) : ORIGIN = 0X38000000, LENGHT = 64K
ITCMRAM (xrw) : ORIGIN = 0X00000000, LENGHT = 64K
I receive correctly smaller packets. There seems to be something limiting the reception as I always correctly receive the same number of bytes