2023-06-02 03:47 AM
I have read the datasheet where this part of ethernet is explained. But I have not clear of all taking it to a practical case.
Case:
I'm wondering what happens with those frames when they achieve MAC controller and the follwing blocks: FIFO and DMA, since FIFO has 2Kbytes, and MAC sends the frame to the DMA by a frame descriptor (struct type). But FIFO are in the middle of these two blocks and I don't know what FIFO does with the DMA descriptor.
So please, let me know if something that I'm go to say is wrong:
My questions:
thanks in advance
2023-06-02 10:56 AM
I'm not sure why you are asking about (or care about) low level Ethernet details when you have HAL/LwIP code that handles all of that. LwIP should take care of buffering the incoming packets (up to the number of buffers that you configured LwIP to use).
Are you having some issue with handling the incoming packets or sending the response packets? Or are you just curious as to how the underlying hardware works?
2023-06-02 11:04 AM
Never mind - I just saw your other 3 or 4 posts about your Ethernet issues.
2023-06-04 11:50 PM
Thanks for your observation.
Because of:
- after some time working fine DMA is owning the Ethernet descriptor for ever and MAC has stopped receiveing data but no frame error is detected.
- HAL could be adding some kind of issues to ethernet communications (they has been reported for lot of users and recognized by technical support).
- Lwip has a lot of configuration parameters related with packet sizes, buffers, etc.. that must be defined. May be my ethernet problems comes from some bad configuration.
Having into account that my data payload is to short, I'm trying to answering who of these 3 parts/blocks (DMA-FIFO-MAC) has the problem and which one. Why do DMA suddenly decide not to free the descriptor to the MAC.
2023-06-04 11:54 PM
As you say I would like to define the number of LwIP buffers correctly and being consistenly with stm32f207 ethernet architecture, behaviour and capability.