Facing issue to create external loader in IAR Workbench

[Harsh_Gajjalwar]

Debug Logs:

Tue Nov 19, 2024 10:46:36: IAR Embedded Workbench 9.50.2 (C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll)
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_M7.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_DBG.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_OB.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_TRACE.dmac
Tue Nov 19, 2024 10:46:37: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H7x5.mac
Tue Nov 19, 2024 10:46:37: Time-limited license - IAR Embedded Workbench for Arm, Cortex-M edition 9.60
Tue Nov 19, 2024 10:46:37: JLINK command: ProjectFile = D:\gitESI\TouchScreenGUI-ESI\EWARM\settings\es10_demo_03_es10_demo_03_CM7.jlink, return = 0
Tue Nov 19, 2024 10:46:37: Device "STM32H745XI_M7" selected.
Tue Nov 19, 2024 10:46:37: DLL version: V7.92l, compiled Oct 25 2023 15:21:06
Tue Nov 19, 2024 10:46:37: Firmware: J-Link V12 compiled Jan 24 2024 12:06:13
Tue Nov 19, 2024 10:46:37: Serial number: 602007946
Tue Nov 19, 2024 10:46:37: JTAG speed is initially set to: 1000 kHz
Tue Nov 19, 2024 10:46:37: ConfigTargetSettings() start
Tue Nov 19, 2024 10:46:37: ConfigTargetSettings() end - Took 17us
Tue Nov 19, 2024 10:46:37: InitTarget() start
Tue Nov 19, 2024 10:46:37: JTAG selected. Identifying JTAG Chain...
Tue Nov 19, 2024 10:46:37: TotalIRLen = 9, IRPrint = 0x0011
Tue Nov 19, 2024 10:46:37: JTAG chain detection found 2 devices:
Tue Nov 19, 2024 10:46:37: #0 Id: 0x6BA00477, IRLen: 04, CoreSight JTAG-DP
Tue Nov 19, 2024 10:46:37: #1 Id: 0x06450041, IRLen: 05, Unknown device
Tue Nov 19, 2024 10:46:37: JTAG Chain Identified. Connecting to DAP TAP...
Tue Nov 19, 2024 10:46:37: Successfully connected to selected DAP TAP.
Tue Nov 19, 2024 10:46:37: DAP initialized successfully.
Tue Nov 19, 2024 10:46:37: Enabling debug in 'Standby', 'Stop' & Sleep mode.
Tue Nov 19, 2024 10:46:37: InitTarget() end - Took 14.4ms
Tue Nov 19, 2024 10:46:37: TotalIRLen = 9, IRPrint = 0x0011
Tue Nov 19, 2024 10:46:37: JTAG chain detection found 2 devices:
Tue Nov 19, 2024 10:46:37: #0 Id: 0x6BA00477, IRLen: 04, CoreSight JTAG-DP
Tue Nov 19, 2024 10:46:37: #1 Id: 0x06450041, IRLen: 05, Unknown device
Tue Nov 19, 2024 10:46:37: DPv0 detected
Tue Nov 19, 2024 10:46:37: AP map detection skipped. Manually configured AP map found.
Tue Nov 19, 2024 10:46:37: AP[0]: AHB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[1]: AHB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[2]: APB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[3]: AHB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[0]: Skipped ROMBASE read. CoreBaseAddr manually set by user
Tue Nov 19, 2024 10:46:37: AP[0]: Core found
Tue Nov 19, 2024 10:46:37: CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Tue Nov 19, 2024 10:46:37: Cache: L1 I/D-cache present
Tue Nov 19, 2024 10:46:37: Found Cortex-M7 r1p1, Little endian.
Tue Nov 19, 2024 10:46:37: FPUnit: 8 code (BP) slots and 0 literal slots
Tue Nov 19, 2024 10:46:37: ROM table scan skipped. CoreBaseAddr manually set by user: 0xE00FE000
Tue Nov 19, 2024 10:46:37: I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way
Tue Nov 19, 2024 10:46:37: D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way
Tue Nov 19, 2024 10:46:37: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Tue Nov 19, 2024 10:46:37: Reset: Reset device via AIRCR.SYSRESETREQ.
Tue Nov 19, 2024 10:46:37: Hardware reset with strategy 0 was performed
Tue Nov 19, 2024 10:46:37: Initial reset was performed
Tue Nov 19, 2024 10:46:37: Found 2 JTAG devices, Total IRLen = 9:
Tue Nov 19, 2024 10:46:37: #0 Id: 0x6BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Tue Nov 19, 2024 10:46:37: #1 Id: 0x06450041, IRLen: 5, Unknown device
Tue Nov 19, 2024 10:46:38: FL/MAC: Cortex-M4 was stopped to ensure safe flashloader operation.
Tue Nov 19, 2024 10:46:38: Loaded debugee: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H7xx_RAM256K.out
Tue Nov 19, 2024 10:46:38: Target reset
Tue Nov 19, 2024 10:46:43: FL/MAC: Cortex-M4 was started.
Tue Nov 19, 2024 10:46:43: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H7x5.mac
Tue Nov 19, 2024 10:46:43: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI.mac
Tue Nov 19, 2024 10:46:43: FL/MAC: Cortex-M4 was stopped to ensure safe flashloader operation.
Tue Nov 19, 2024 10:46:43: FL/MAC: Configuring QUADSPI GPIO pins.
Tue Nov 19, 2024 10:46:43: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI.mac(88,7): Error: Unknown or ambiguous symbol. use_qspi_bk2_ncs
Tue Nov 19, 2024 10:46:43: Error while calling macro execUserFlashInit
Tue Nov 19, 2024 10:46:43: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI.mac
Tue Nov 19, 2024 10:46:43: Failed to load flash loader: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI_test.flash
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_M7.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_DBG.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_OB.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_TRACE.dmac
Tue Nov 19, 2024 10:46:50: Loading the J-Link Driver driver
Tue Nov 19, 2024 10:46:50: IAR Embedded Workbench 9.50.2 (C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll)

[Harsh_Gajjalwar]

I'm trying to create a custom QSPI flash loader in IAR Embedded Workbench 9.2 for an STM32H7 microcontroller. I'm referring to the following existing loader:

C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\src\flashloader\ST\FlashSTM32H7xx_QSPI

However, I need to configure the correct QSPI pins (e.g., clock, IO lines, chip select) for my hardware. Normally, these configurations are available in the .ioc file when working with STM32CubeMX, but I'm not sure how to integrate this information into the IAR flash loader.

My Questions:

1. Where can I find the pin configuration (e.g., .ioc file or other resources) for the default IAR QSPI flash loader?
2. If I need to create my own pin configuration, how should I update the loader code? Are there specific macros or registers I should modify?
3. Is there a recommended workflow for generating a QSPI flash loader using both STM32CubeMX and IAR?

---

My Environment:

• MCU: STM32H745
• Toolchain: IAR Embedded Workbench 9.2
• Flash Device: MT25QL512A (QSPI)

Any guidance or resources to properly configure the QSPI pins and integrate them into the IAR flash loader would be greatly appreciated. Thank you in advance!

[Tesla DeLorean]

This is like the third post on the same topic. For IAR support go to IAR. Or read their related documentation or examples.

Seem to recall the .flash is a .ELF with initialization function to configure the pins.

Expect you're going to need to initialize in basic HAL level code, and the Cube tools are not going to auto-gen the code for you.

Check MSP code generated for your app or your BSP level code. Or Driver BSP type code examples for the DISCO or EVAL boards.

[Andrew Neil]

You're going to need to ask IAR what their logs mean!

https://www.iar.com/sv/knowledge/support/