STM32H745XI : Data from Backup SRAM getting lost on power cycle

[shravanhudekar]

 I'm trying to use the 4K backup RAM on the STM32H745XI. Using following code initialize RTC and backup domain. VBAT of 3V coin cell is used power RTC backup domain on VDD off. 

HAL_PWR_EnableBkUpAccess();
      while ((PWR->CR1 & PWR_CR1_DBP) == RESET)
      {
      }
      __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);

      /** Initializes the RCC Oscillators according to the specified parameters
      * in the RCC_OscInitTypeDef structure.
      */
     /*
     */
      if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
      {
        Error_Handler();
      }
    MX_RTC_Init();
    __HAL_RCC_BKPRAM_CLK_ENABLE();
    if(!HAL_PWREx_EnableBkUpReg())
    {
        printf("Backup SRAM ready\r\n");
    }
}
following code is used to read and write
// write to backup RAM
memcpy(*(__IO uint8_t *)D3_BKPSRAM_BASE,(uint8_t *)&w_data, sizeof(w_data));

//read from backup RAM
memcpy(*(__IO uint8_t *)D3_BKPSRAM_BASE,(uint8_t *)&r_data, sizeof(r_data));

The RTC is working and keeps time even on power off and restart, so I know the battery system is OK. I can read and write to the backup RAM OK but it loses all data on power off.

No RDP or temper detection is enabled in my case.

[waclawek.jan]

In your first post you gave also this information:

On VDD I am able to read and write on SRAM successfully and even on soft reset data is not lost.

but when device goes into power down (VBAT connected to RTC) data is lost when checked on next power cycle.

RDP, tamper detection and cache is disabled.

I honestly don't know what to recommend: as you've seen in that thread, it was about switching on the low-power regulator and avoiding caching pitfalls, but you appear to have catered for that. I don't use Cube so can't judge whether those functions indeed do what they promise - you should check at register level yourself.

> even on soft reset data is not lost

That would exclude caching and similar issues. RTC is working (which I assume means also that time is properly advanced during VDD being off) means that VBAT is connected. IMO the only remaining thing is the low-power regulator not being actually switched on - as I've said, check by reading back the respective registers and check against RM.

JW