Sram not working if writing in eprom with spi

[SGasp.1]

Hi community..

I am working with mcu STM32F429 and SRAM with code IS42S16400J .

I have developed a code for init and working with this sram and it was working

void SDRAM_Init(void) 
{ 
        volatile uint32_t ptr = 0; 
        volatile uint32_t i = 0; 
 
        /* PB5,PB6 */ 
        GPIOB -> MODER |= ((GPIOB -> MODER) & 0xFFFFC3FF ) | 0x00002800;         // AF Function 
        GPIOB -> OTYPER |= ((GPIOB -> OTYPER) & 0xFFFFFF9F);                                // Push-Pull 
        GPIOB -> OSPEEDR |= ((GPIOB -> OSPEEDR) & 0xFFFFC3FF) | 0x00003C00;        // Very High Speed 
        GPIOB -> PUPDR |= ((GPIOB -> PUPDR) & 0xFFFFC3FF);                                        // No Pull-Up 
        GPIOB -> AFR[0] |= ((GPIOB -> AFR[0]) & 0xF00FFFFF) | 0x0CC00000;        // 
        GPIOB -> AFR[1] |= ((GPIOB -> AFR[1]) & 0xFFFFFFFF) | 0x00000000;        // 
 
        /* PC0 */ 
        GPIOC -> MODER |= ((GPIOC -> MODER) & 0xFFFFFFFC) | 0x00000002;         // AF Function 
        GPIOC -> OTYPER |= ((GPIOC -> OTYPER) & 0xFFFFFFFE);                                // Push-Pull 
        GPIOC -> OSPEEDR |= ((GPIOC -> OSPEEDR) & 0xFFFFFFFC) | 0x00000003;        // Very High Speed 
        GPIOC -> PUPDR |= ((GPIOC -> PUPDR) & 0xFFFFFFFC);                                        // No Pull-Up 
        GPIOC -> AFR[0] |= ((GPIOC -> AFR[0]) & 0xFFFFFFF0) | 0x0000000C;        // 
        GPIOC -> AFR[1] |= ((GPIOC -> AFR[1]) & 0xFFFFFFFF) | 0x00000000;        // 
 
        /* PD0,PD1,PD8,PD9,PD10,PD14,PD15 */ 
        GPIOD -> MODER |= ((GPIOD -> MODER) & 0x0FC0FFF0) | 0xA02A000A;         // AF Function 
        GPIOD -> OTYPER |= ((GPIOD -> OTYPER) & 0xFFFF38FC);                                // Push-Pull 
        GPIOD -> OSPEEDR |= ((GPIOD -> OSPEEDR) & 0x0FC0FFF0) | 0xF03F000F;        // Very High Speed 
        GPIOD -> PUPDR |= ((GPIOD -> PUPDR) & 0x0FC0FFF0);                                        // No Pull-Up 
        GPIOD -> AFR[0] |= ((GPIOD -> AFR[0]) & 0xFFFFFF00) | 0x000000CC;        // 
        GPIOD -> AFR[1] |= ((GPIOD -> AFR[1]) & 0x00FFF000) | 0xCC000CCC;        // 
 
        /* PE0,PE1,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15 */ 
        GPIOE -> MODER |= ((GPIOE -> MODER) & 0x00003FF0) | 0xAAAA800A;         // AF Function 
        GPIOE -> OTYPER |= ((GPIOE -> OTYPER) & 0xFFFF007C);                                // Push-Pull 
        GPIOE -> OSPEEDR |= ((GPIOE -> OSPEEDR) & 0x00003FF0) | 0xFFFFC00F;        // Very High Speed 
        GPIOE -> PUPDR |= ((GPIOE -> PUPDR) & 0x00003FF0);                                        // No Pull-Up 
        GPIOE -> AFR[0] |= ((GPIOE -> AFR[0]) & 0x0FFFFF00) | 0xC00000CC;        // 
        GPIOE -> AFR[1] |= ((GPIOE -> AFR[1]) & 0x00000000) | 0xCCCCCCCC;        // 
 
        /* PF0,PF1,PF2,PF3,PF4,PF5,PF11,PF12,PF13,PF14,PF15 */ 
        GPIOF -> MODER |= ((GPIOF -> MODER) & 0x003FF000) | 0xAA800AAA;         // AF Function 
        GPIOF -> OTYPER |= ((GPIOF -> OTYPER) & 0xFFFF07C0);                                // Push-Pull 
        GPIOF -> OSPEEDR |= ((GPIOF -> OSPEEDR) & 0x003FF000) | 0xFFC00FFF;        // Very High Speed 
        GPIOF -> PUPDR |= ((GPIOF -> PUPDR) & 0x003FF000);                                        // No Pull-Up 
        GPIOF -> AFR[0] |= ((GPIOF -> AFR[0]) & 0xFF000000) | 0x00CCCCCC;        // 
        GPIOF -> AFR[1] |= ((GPIOF -> AFR[1]) & 0x00000FFF) | 0xCCCCC000;        // 
 
        /* PG0,PG1,PG4,PG5,PG8,PG15 */ 
        GPIOG -> MODER |= ((GPIOG -> MODER) & 0x3FFCF0F0) | 0x80020A0A;         // AF Function 
        GPIOG -> OTYPER |= ((GPIOG -> OTYPER) & 0xFFFF7ECC);                                // Push-Pull 
        GPIOG -> OSPEEDR |= ((GPIOG -> OSPEEDR) & 0x3FFCF0F0) | 0xC0030F0F;        // Very High Speed 
        GPIOG -> PUPDR |= ((GPIOG -> PUPDR) & 0x3FFCF0F0);                                        // No Pull-Up 
        GPIOG -> AFR[0] |= ((GPIOG -> AFR[0]) & 0xFF00FF00) | 0x00CC00CC;        // 
        GPIOG -> AFR[1] |= ((GPIOG -> AFR[1]) & 0x0FFFFFF0) | 0xC000000C;        // 
 
        RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; 
 
        // Initialization step 1 
        FMC_Bank5_6->SDCR[0] = FMC_SDCR1_SDCLK_1  | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE_1; 
        FMC_Bank5_6->SDCR[1] = FMC_SDCR1_NR_0          | FMC_SDCR1_MWID_0 | FMC_SDCR1_NB | FMC_SDCR1_CAS; 
        // Initialization step 2 
        FMC_Bank5_6->SDTR[0] = TRC(7)  | TRP(2); 
        FMC_Bank5_6->SDTR[1] = TMRD(2) | TXSR(7) | TRAS(4) | TWR(2) | TRCD(2); 
 
        // Initialization step 3 
        while(FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); 
        FMC_Bank5_6->SDCMR          = 1 | FMC_SDCMR_CTB2 | (1 << 5); 
        // Initialization step 4 
        for(i = 0; i  < 1000000; i++); 
        // Initialization step 5 
        while(FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); 
        FMC_Bank5_6->SDCMR          = 2 | FMC_SDCMR_CTB2 | (1 << 5); 
        // Initialization step 6 
        while(FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); 
        FMC_Bank5_6->SDCMR          = 3 | FMC_SDCMR_CTB2 | (4 << 5); 
        // Initialization step 7 
        while(FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); 
        FMC_Bank5_6->SDCMR          = 4 | FMC_SDCMR_CTB2 | (1 << 5) | (0x231 << 9); 
        // Initialization step 8 
        while(FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); 
        FMC_Bank5_6->SDRTR |= (683 << 1); 
        while(FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); 
        // Clear SDRAM 
//        for(ptr = SDRAM_BASE; ptr < (SDRAM_BASE + SDRAM_SIZE); ptr += 4) 
//                        *((uint32_t *)ptr) = 0x07e007e0; 
//        for(ptr = SDRAM_BASE; ptr < (SDRAM_BASE + 959); ptr += 4) 
//                        *((uint32_t *)ptr) = 0xFFFFFFFF; 
        for(ptr = SDRAM_BASE; ptr < (SDRAM_BASE + 0xc7ff); ptr += 4) 
                        *((uint32_t *)ptr) = 0x07e007e0; 
        for(ptr = SDRAM_BASE + 0xc800; ptr < (SDRAM_BASE + 0x18fff); ptr += 4) 
                        *((uint32_t *)ptr) = 0xf800f800; 
        for(ptr = SDRAM_BASE + 0x19000; ptr < (SDRAM_BASE + SDRAM_SIZE); ptr += 4) 
                        *((uint32_t *)ptr) = 0x001f001f; 
}

Then we decided to use an external eeprom for saving some parameters using the following chip AT25640..

I developed the code in a separated project by using the HAL SPI for communicating and saving the parametrs and it was working.

/**
  * @brief  Function for writing the eeprom
  * @param  *spi2Handle
  * @param  *txBuffer
  * @param  size
  * @param  addr
  * @retval EEPROM_ERROR or EEPROM_OK
  */
uint8_t WriteEEPROM(SPI_HandleTypeDef *spi2Handle, uint8_t *txBuffer, uint16_t size, uint16_t addr)
{
 
	uint8_t addrLow = addr & 0xFF;
	uint8_t addrHigh = (addr >> 8);
 
	uint8_t wrenInstruction = WREN_EEPROM;
 
	uint8_t buffer[32] = {WRITE_EEPROM, addrHigh, addrLow};
 
	for(uint8_t i = 0 ; i < size ; i++)
	{
		buffer[3+i] = txBuffer[i];
	}
 
	/*chip select*/
	HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, RESET);
 
	if(HAL_SPI_Transmit(spi2Handle, &wrenInstruction, 1, TIMEOUT_EEPROM) != HAL_OK)
	{
		return EEPROM_ERROR;;
	}
 
	/*chip select*/
	HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, SET);
 
	/*delay in ms*/
	HAL_Delay(10);
 
	/*chip select*/
	HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, RESET);
 
	if(HAL_SPI_Transmit(spi2Handle, buffer, (size + 3), TIMEOUT_EEPROM) != HAL_OK)
	{
		return EEPROM_ERROR;
	}
 
	/*delay in ms*/
	HAL_Delay(10);
 
	/*chip select*/
	HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, SET);
 
	return EEPROM_OK;
}

When I have imported this function within the project with the init of the sram the sram was not working anymore..

I really i don't understand why an init function is not working by calling the hal spi transmit for writing in eeprom ?

Any idea ?

Do you see something wrong in the init of the code of the sram?

Thanks a lot

[Andrew Neil]

"the sram was not working anymore"

What, exactly, does that mean?

Are you getting no activity at all on the interface lines?

Is the timing messed-up?

other ... ?

[SGasp.1]

It is conncted with a display.. the display it is not working..

Display is blank and it is not possible to see nothing

[Andrew Neil]

So why do you say that the SRAM is not working?

How do you know it's not just the Display that's stopped working?

Or, perhaps, it's both?

And what does "not working" mean?

• Nothing at all on the display?
• Rubbish on the display?
• Other ... ?

Again, have you looked at the interface lines to see what's actually happening in the hardware?

[SGasp.1]

Display is blank.. Nothing at all

[Andrew Neil]

So, again, why do you say that the SRAM is not working?

And, again, have you looked at the interface lines to see what's actually happening in the hardware?

[SGasp.1]

It is not clear to me the connection between the sram init and the hal spi transmit.. The display for sure it is using the sram