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New batch STM32F051 LSE don't start

passafabio2
Associate III

A new batch of electronic board mount an STM32F05R8T6

AA170 9U

TWN AA 131 marked.

All of this devices don't start up LSE clock.

The code is the same for about five years and makes the LSE clock start up till this days correctly. The initialization was made using example code bundled with discovery stm32F051.

I create with CubeIDE Version: 1.9.0 a minimal setup (CubeMX) for initializa internal RC but the code hangs on

while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
   {
    if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
    {
     return HAL_TIMEOUT;
    }
   }

The quartz is the same sice five years and i try to modify the capacitor from 15nF to 6,8nF with no success.

Same board with STM32F05R8T6

GQ272 9U

CHN GQ 944 marked

run perfectly.

Any ideas?

Thanks 

Fabio

1 ACCEPTED SOLUTION

Accepted Solutions
passafabio2
Associate III

The problem seem the poor cleaning made by manufacturer when they find a Sn join between the 32Khz768 quartz pins. Fixing the unwanted join with soldering wire they don't clean well the water based flux and in some occasions made a lower impededence which makes quartz unable to run. The quartz with soldered join is covered with a 16X2 lcd display then detected dirty pin wasn't immediate.
The first batch of stm32f051RBT8 was more strong in oscillating.

Fabio

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35 REPLIES 35
TDK
Guru

If you increase RCC_LSE_TIMEOUT_VALUE, does it work?

If you scope LSE, do you see a signal?

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passafabio2
Associate III

Doubled the value from 5000 to 10000 but nothing change...

A good board programmed with the test code for LSE created with CubeMx corectly goes over the init and chek functionality of LSE, light on a led done by a successive code..

> 15nF to 6,8nF

Double-check the capacitors, they surely must not be in the nF range.

Also, how exactly is VBAT connected?

Write a simple test program, which does nothing but

  • enables backup domain access by setting PWR_CR.DBP (note that PWR clock has to be set in RCC prior to this)
  • resets backup domain using RCC_BDCR.BDRST
  • enables LSE by setting RCC_BDCR.LSEON
  • waits undefinitely until RCC_BDCR.LSERDY is set
  • lights up a LED or indicates success in some other suitable way

Note, that LSE startup times in several seconds (say up to 10s) is completely normal.

In this program, try also different RCC_BDCR.LSEDRV settings.

JW

passafabio2
Associate III

Sorry my mistake, I wanted to say 15pF to 6,8pF

STM32F05R8T6 ?? or STM32F051R8T6 STM32F058R8T6

Can you read the device ID from the part, to be sure of the die/stepping ?

DBGMCU->IDCODE

Might need lower capacitance.

There should be a means to measure/export the LSE clock without probing directly.

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passafabio2
Associate III

STM32F051R8T6

AA170 9U

TWN AA 131

IDCODE 0x20006440

while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)

Is the flag which manage the running/halt state ol LSE clock.

I mean with an oscilloscope or TIM peripheral vs HSE clock​

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@Imen DAHMEN​ @Amel NASRI​  Please check if any settings or performance changes occurred with respect to LSE clocking

The 0x2000 stepping is not covered in RM0091 Rev 9 (Jan 2017)

https://www.st.com/resource/en/reference_manual/rm0091-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

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passafabio2
Associate III

Today I tried using 3,9pF cap (the only I have in my warehouse) with no success....