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Bypass Capacitors on NUCLEO-H723

gigtrent
Associate

I am trying to design my own board using the STM32H723ZGT and using the nucleo schematic as a guide. I believed 100nf was typical for the VDD pin bypass capacitors however there is one pin(pin 62) with a 4.7uf capacitor instead. I understand the VBAT and VDDA pins having a different values but why is the C60 bypass capacitor this much bigger bigger? thankyouScreenshot 2024-09-09 201627.png

1 ACCEPTED SOLUTION

Accepted Solutions
STTwo-32
ST Employee

Hello @gigtrent and welcome to the ST Community 

As mentioned on the part 7.4 of the AN5419:

"All the power supply and ground pins must be properly connected to the power supplies. These connections,
including pads, tracks and vias should have lowest possible impedance. This is typically achieved with thick track
widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (100 nF) and one single
ceramic capacitor (min. 4.7 μF) connected in parallel. These capacitors need to be placed as close as possible to,
or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact
values depend on the application needs."

STTwo32_0-1725958714939.png

Best Regards.

STTwo-32

 

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

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3 REPLIES 3
STTwo-32
ST Employee

Hello @gigtrent and welcome to the ST Community 

As mentioned on the part 7.4 of the AN5419:

"All the power supply and ground pins must be properly connected to the power supplies. These connections,
including pads, tracks and vias should have lowest possible impedance. This is typically achieved with thick track
widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (100 nF) and one single
ceramic capacitor (min. 4.7 μF) connected in parallel. These capacitors need to be placed as close as possible to,
or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact
values depend on the application needs."

STTwo32_0-1725958714939.png

Best Regards.

STTwo-32

 

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

SofLit
ST Employee

Hello @gigtrent and welcome to the community.

Decoupling/Bypass capacitors is HW recommendation and not only restricted to STM32 MCUs but to digital circuits: 

https://components101.com/articles/decoupling-capacitor-vs-bypass-capacitors-working-and-applications

https://www.quora.com/What-is-the-purpose-of-using-two-capacitors-a-small-value-electrolytic-and-a-large-ceramic-as-decoupling-bypass-in-power-supplies:

Does it represent an issue for you?

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

HI STTwo-32, this is great thankyou I've had a bit of trouble finding the AN for this series this is a massive help. Cheers