About the USB trace impedance needs in device mode

[Kura]

I'm referring to USB hardware and PCB guidelines using STM32 MCUs (AN4879)

and to USB 2.0 specification. MCU is STM32H755

In case when Embedded pull-up resistor on USB_DP line, USB 2.0 OTG HS controller with embedded on-chip HS PHYs and mode = device mode:

There (AN4879) were not mentioned about the USB DP or DM impedance or clearance needs, referred only to USB specification. In addition nothing in AN4938. Some manufacturers gives their recommendations to high-speed PCB designs, including USB for some materials. But not found any ST's document about that(?)

• So the general USB 2.0 high-speed rate differential trace impedance 90 Ω +/- 15% is correct?

I ask because think to need some confirmation before the implementation. Thanks in advance.

[Singh.Harjit]

That is the correct target. The trace width and spacing will be a function of the board's dielectric constant, stack up, and reference plane / trace structure. There are online calculators but those are just an approximation. After you get your boards, think about using a TDR and measuring the traces. You can also ask your board house to do this for you.

[K.Ata15]

ST had published some sch and pcb files for older disco/eval boards and if i remember correctly those are impedance matched to 100 mil. As the USB speed is still super slow in newer chips, this should do i guess.

[Kura]

Thanks, I will impelent with 90 Ω. The clearance can be calculated.

[Kura]

.

[Kura]

Actually I have read the schematic of NUCLEO-H743ZI. There were commented the ST-LINK chip USB differential impedance (85-95), and the MCU USB-mode is on that board may dual mode because there is some switch implemented to bus.

The high speed is on H755 is 480 Mb/s, which is the default when microB plug is connected.

But thanks any way.

[K.Ata15]

wasn't the internal USB PHY only 12 Mbps, to achieve 480 Mbps you need external chip ?

[Kura]

Excellent point. The integrated HS PHY supports only full speed, not high speed.