2024-05-28 06:54 PM
Hi, I'm working on a project and have a question for you
First, ARC mode is said to increase the radius of X and Y axis of wireless charging by up to 50%.
1. why is it CFG register, is the mode always active?
2.the setting value is steps of 10mV and I wonder what is the relationship between this and ARC mode?
3.GUI related question, how can I take memh files of CFG files and patch files and convert them to hex code and update them to firmware?
I have implemented the firmware update, but I want to update it with data from files created in the GUI.
Solved! Go to Solution.
2024-05-29 02:35 AM
Hi park
Please check AN
Q1. why is it CFG register, is the mode always active?
A1: During the initial phase of the power transfer STWLC38 operates in ARC mode, ST’s proprietary mode, which
makes the power-up sequence smoother and more reliable. For more information, see Section 5.12 Adaptive
rectifier configuration (ARC) mode .
Once the VRECT voltage rises high enough, the internal power management system starts operating. The digital
core is powered up and ready to control the internal circuitry. Default device settings are used until the digital core
is woken up after which the firmware loads settings saved in the Cofiguration file saved in NVM. The device is
now ready to operate
Q2.the setting value is steps of 10mV and I wonder what is the relationship between this and ARC mode?
A2:When rx vrect > 6V it will disable arc mode
Q3.GUI related question, how can I take memh files of CFG files and patch files and convert them to hex code and update them to firmware?
A3: use gui head generate or check AN document.
2024-05-29 02:35 AM
Hi park
Please check AN
Q1. why is it CFG register, is the mode always active?
A1: During the initial phase of the power transfer STWLC38 operates in ARC mode, ST’s proprietary mode, which
makes the power-up sequence smoother and more reliable. For more information, see Section 5.12 Adaptive
rectifier configuration (ARC) mode .
Once the VRECT voltage rises high enough, the internal power management system starts operating. The digital
core is powered up and ready to control the internal circuitry. Default device settings are used until the digital core
is woken up after which the firmware loads settings saved in the Cofiguration file saved in NVM. The device is
now ready to operate
Q2.the setting value is steps of 10mV and I wonder what is the relationship between this and ARC mode?
A2:When rx vrect > 6V it will disable arc mode
Q3.GUI related question, how can I take memh files of CFG files and patch files and convert them to hex code and update them to firmware?
A3: use gui head generate or check AN document.
2024-05-30 02:20 AM
thanks!