L6234 Vref capacitor

[marek23]

Posted on April 04, 2013 at 20:26

The AN1088 app note states:

�

Vref ( Voltage Reference).

This is the internal 10V voltage reference pin to bias the logic and the low voltage circuitry of the device. A 1

m

F electrolytic capacitor connected from this pin to GND ensures the stability of the DMOS drive circuit. This pin can be externally loaded up to 5mA. Figure 3 and 4 show the typical behavior of the Vref pin.�

I was wondering whether a higher value ceramic capacitor can be used in place of the 1uF electrolytic capacitor on the Vref pin. For example, can we use a 4.7uF, 25V, ceramic, such as  C1608JB1E475K080AC? The app note does not describe whether there are other capacitor options. Thanks! #l6234-an1088

[Enrico Poli]

Posted on April 10, 2013 at 17:21

The VREF capacitor can be ceramic, but its value should be >= of 1uF.

So the capacitor you indicated is OK.RegardsEnrico

[MQi.1]

I read from datasheet "10 V external reference available", while I tested 8.8v at Vref by a 12v battery source, could I added an external 10v to this pin?

[AScha.3]

> "10 V external reference available", while I tested 8.8v at Vref by a 12v battery

from ds:

So at 12V supply about 8.8 V are exactly what it should be.

[MQi.1]

So what does "external reference" mean? does it mean a reference came from outside or it could be a reference for external components?

[MQi.1]

And, I found there is a downward arrow under "external reference" block in block diagram on page 3 of DocID1107 Rev 11(L6234 datasheet), and there is also a downward arrow under each drive gate of the 3 down DMOS, are they connected internally?

[AScha.3]

>So what does "external reference" mean? does it mean a reference came from outside or it could be a reference for external components?

it could be used as reference for external components .

>And, I found there is a downward arrow under "external reference" block in block diagram on page 3 of DocID1107 Rev 11(L6234 datasheet), and there is also a downward arrow under each drive gate of the 3 down DMOS, are they connected internally?

Obviously this is Vdd for the lo-side drivers and the carge pump ; VBOOT is for the hi-side drivers.