problem with port1.13 : HDLC

[christophe239955]

Posted on January 24, 2006 at 06:23

problem with port1.13 : HDLC

[christophe239955]

Posted on January 19, 2006 at 11:24

we want to use the HCLK for the HDLC clock (FM0 in asynchronous with DPLL for Rx) :

we are configuring one timer in output alternate PUSH PULL GPIO_Config(GPIO0,0x2000,GPIO_AF_PP); RCCU_PCLK(RCCU_RCLK_4); TIM_Init(TIM2);........ TIM_ClockSourceConfig(...); TIM_PrescalerConfig(...); TIM_PWMOModeConfig... + we configure the receiver and the Xmit to use the PLL2 with the RCCU_PLL2Config(RCCU_PLL2_Mul_16,RCCU_Div_1); HDLC_XmitClockSourceConfig(HDLC_HTXCKSource); HDLC_XmitBaudrateConfig(7); HDLC_RecvClockSourceConfig(HDLC_HRXCK); HDLC_RecvClockPrescalerConfig(0); But without doing the connection between port1.13 and port of the timer 0, we have a signal which is going out from P1.13 : which must be in???????????????????????? Thanks for explaining why we have a signal on this input 1.13? Is it possible to use the HCLK in FMO with DPLL?

[davidbellegarde9]

Posted on January 24, 2006 at 06:23

This signal which appears on the P1.13 pin is a perturbation (about 100mV and same frequency as the HRXD) made by the HRXD pin. With the FM0 coding, no data to transmit creates 2 edges by bit. And this signal perturbs the nearest pin which is P1.13.

You could check this with the NRZI coding, the perturbation will occur only when there will be a transmission. To avoid this, either you put P1.13 as a GPIO_AF_PP or you could shroud the HRXD line.