How can I maximize or optimize the range of voltages the ADC can sample for a highly sensitive system?

[SCutl.1]

Let me start by providing a little background on my project. I'm working on developing an avalanche transceiver. For those of you who are unfamiliar with avalanche transceivers, an avalanche transceiver is a search and rescue device used to help locate buried avalanche victims. A transceiver in transmit mode sends a 457kHz pulse for ~70ms every (depending on the model) 400-800ms. This generates an electromagnetic flux pattern that can be detected by a transceiver in receive mode. Modern transceivers are equipped with 2 or more ferrite rod loopstick antennas.

Currently my design consists of a loopstick antenna feeding an AD8310 logarithmic amplifier. The log amp is needed because the emitted signal falls off exponentially as a receiver moves away from the transmitter. The output voltage (VOUT) of the AD8310 ranges from 0.4V to ~2.6V. From what I can tell this output range pairs nicely with the input range of the ADCs on STM32 ADCs. However, the ferrite rod loopstick antennas are highly susceptible to noise coming from cellphones, radios, etc. So my plan was to feed AD8310's VOUT through an active low-pass filter with a gain of ~2 to clean up the signal as much as possible and extend the range of VOUT from 0.8V to ~5.2V. My thought was that the wider output range would help the firmware differentiate changes in true signal strength vs signal noise. But if the STM32's ADC input ranges from 0V to 3.6V, then the gain from the low-pass filter is useless, right? Is there any way to extend the input range of the ADC? Or is my thought process way off? Are there any other options?

Thanks for taking the time to read this and happy holidays!

[Ozone]

> But if the STM32's ADC input ranges from 0V to 3.6V, ...

Not exactly.

The input ranges from 0 to +Vref, the latter equaly Vdda at max (which is +3,6V, and the absolute maximal rating).

ST says the following about VDD/VDDA relations:

It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation.

Taken from the F40x datasheet s example.

>... and extend the range of VOUT from 0.8V to ~5.2V

Not sure if I understand what you mean here, but the STM32 ADCs cannot deal with negative voltages.

Perhaps an external preamplifier and ADC with wider and symmetrical input range would be an option.

> A transceiver in transmit mode sends a 457kHz pulse...

Not sure if I understand this correctly. Do you want to sample this RF signal ?

You could surely satisfy the Nyquist criterion, but not much margin left.

[SCutl.1]

I'm sorry. I made some typo errors. All of the "~" characters were supposed to be printed as the tilde character which I meant as approximate values. So in other words, "0.8V to ~5.2V" was supposed to mean "0.8V to approximately +5.2V" and "~70ms" was supposed to mean "approximately 70ms."

The ADC shouldn't sample the 457kHz signal directly unless there's some way to write the firmware to interpret a large snapshot of the received signal data. The firmware would need to calculate the input power (in dBV or dBm) from each dataset (obtained by the ADC) from every 70ms pulse of the transmitter and then calculate some distance between transmitter and receiver from the calculated power level. I'm sure there's a way to do that but I don't think I'm smart enough :face_with_tears_of_joy: This is where the AD8310 IC comes in for RSSI. The receiver antenna feeds it's signal into the inputs (high and low) of the AD8310, which acts as a power meter and outputs a voltage (0.4V to 2.6V) based on the power delivered by the 457kHz pulse. The output voltage of the AD8310 still has a lot of noise (because of the magnetic properties of the antenna) even though it should look like a clean square wave with an uptime of 70ms and downtime of 400ms. The low-pass filter would ideally clean up all the noise in that square wave, and then the ADC would sample from the cleaned up square wave from the output of the low-pass filter. The firmware (on the microcontroller of the receiver) could then use the samples from the ADC to determine some distance to the transmitter (not entirely sure what the relationship is between ADC sampled value and distance is yet) and display that distance to the user of the transceiver.

Based on my understanding of the Nyquist criterion, I think the sample rate in any microcontroller's ADC is WAY more than enough. The period of the square wave would be 470ms to 870ms depending on the model/manufacturer of the avalanche beacon.

So my idea behind increasing the range of voltages that the ADC could accept as inputs was just an extra helper (on top of the low-pass filter) for the firmware to detect changes in signal strength. Even though the low-pass filter eliminates a lot of noise, it's not 100% effective.

[Michael K]

This is unrelated to your question, but the tilde characters appear correctly as tilde characters on my 4k monitor, but appear as dashes on my 1080p monitor. Strange!

Best of luck on your project!

[SCutl.1]

Very strange. They're all displaying correctly on my screen now too.

[Ozone]

> The ADC shouldn't sample the 457kHz signal directly unless there's some way to write the firmware to interpret a large snapshot of the received signal data.

I suggest to carefully read the datasheet of some MCUs that might be qualified.

Referring the same F40x, the ADC has a max. sample rate of 2Msps, or 3,75Msps in dual mode, or 6Msps in triple mode. Which means, two or three channels of different ADC connected to the same input to increase throughput. Other MCUs achieve a somehow higher speed (7,2Msps in triple mode for the F74x).

Assuming 2Msps, that would by about 4 samples per period at a 457kHz rate.

Second point is RAM size. A 870ms period would produce about 400.000 samples per period, or about 800kB.

So you would need to work on sub-sets.

> Based on my understanding of the Nyquist criterion, I think the sample rate in any microcontroller's ADC is WAY more than enough. The period of the square wave would be 470ms to 870ms depending on the model/manufacturer of the avalanche beacon.

I suppose that requires a envelope generation in hardware.

Higher BOM costs, but much reduced data throughput and performance requirements.

A sample rate of a few kHz would probably suffice, and easily be manageable where performance and resource are concerned.

For the analog section, I am not really a hardware expert. But you could amplify the signal to any appropriate level, do a LP filtering and delimiting, and shift the signal to the ADC input range.