2006-02-27 10:43 AM
HDLC Clarification - Buffer Access Width
2006-02-25 04:35 PM
Regarding the HDLC TX and RX buffer access support.
Every other 32bit APB register we are warned to only operate on as 32 bits. HDLC RX/TX buffers are described in the reference manual as 32 bits (Although the addresses in Figure 79 of the Nov reference manual incorrectly show xxxfh instead of xxxch). But no where does it describe allowable access for read and write. I note the HDLC Library example uses 8 bit reads and 32 bit writes. Then an FAE advises 16 bit operations are most efficient. Can ST issue a definitive statement about the allowed read and write accesses (8,16 or 32 bit) to these registers? I am loathed to use the HDLC library as a reference as even by reading it I have found bugs (seperate post) that show it is obviously not well tested if tested at all.2006-02-27 02:51 AM
Almost of all the IPs on the APB are using 16-bit access, except EIC. Furthermore, the APB should handle 16-bit to 32-bit access or another kind of access. For the HDLC RAM, you can write in with 32-bit access.
2006-02-27 10:43 AM
I am unsure about your answer becasue it contradicts so much of what is in the reference manual.
You Say- Almost of all the IPs on the APB are using 16-bit access, except EIC Manual Says The APB Bridge registers MUST be accessed with 32-bit aligned operations (i.e. no byte/half word cycles are allowed). So here is another case where manual says 32 bits is comulsory. You say the APB should handle 16-bit to 32-bit access or another kind of access Manual says Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 16-bit words. Byte or bit-wise access is not allowed. Also the HDLC.C Example only does 32bit writes to the HDLC buffer and this takes a bit of effort as they are copying non aligned to aligned data. So thanks for you assistance but we need authoritive answer from ST I think.