Posted on February 14, 2005 at 09:37Mmmm. I read your question but I found something strange.
First of all, which device are you using?
You say you want to use three chip select lines. I guess you phisically have three memory banks. Have you configured properly RPOH register? To use CS0,CS1 and CS2 lines you have to set CSSEL in 00 or 11 configuration (also CS3 and CS4) . Moreover you cannot use an arbitrary number of P4 lines, for example if you want to have 1Mbytes of address space and you want to use CAN you have to choose 00 configuration for SALSEL (A0...A19). In that way, using three CS signals you can address up to 3 Mbytes (or 5 Mbytes with 5 CS).
Regarding ADDRSELx I want to remind you that there is a kind of priority. The window selected by ADDRSEL2 has more priority than the window selected by ADDRSEL1 and all other space is managed by CS0.
So for istance, you can create three windows (1Mega size) completely separated in this way:
2)Set ADDRSEL1=0x1008 (1mega starting from 0x100000), CS1 will be low in this window.
2)Set ADDRSEL2=0x2008 (1mega starting from 0x200000), CS2 will be low in this window.
Set BUSCON0, BUSCON1 and BUSCON2 according to the carachteristics of your memory. All the space that is not managed by CS1 and CS2 is assigned to CS0 (first megabyte).
You can also set ADDRSEL1 and ADDRSEL2 setting ADDRSEL1=0x0805 (128K starting from 0x080000) and ADDRSEL2=0x0904 (64K starting from 0x090000). The lowest nibble of ADDRSELx specifies the window size, 0 identifies 4K size. Note that ADDRSEL2 overlaps ADDRSEL1. As before all the remaining addressable space is managed by CS0.
Remember also that setting in BUSCONx CSRENx=0 and CSWENx=0, ''..address chip select signals remain active until an access to another address window. An address chip
select becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a different address area.''
