EMI handshake isgnal

[arifbalci]

Posted on September 08, 2006 at 15:12

EMI handshake isgnal

[arifbalci]

Posted on May 17, 2011 at 09:30

I will use the STR91x family with external Devices. FGPA uses external RAM shared with uC. In this case is needed the handshake pins e.g. nWAIT or READY signals. Is it implemented in the STR91x family.

Regards

[spurious]

Posted on May 17, 2011 at 09:30

You can use one of the external interrupt pins on STR9.

What is the use of upper and lower byte select signals (WRL and WRH) on STR9 if no general WR pin is available? SRAMS have 3 pins for such purpose UB, LB and WR. How to connect such 16bit SRAM to STR9? And to read 32bit value two reads must be issued? What about accessing address that is not aligned to 16bits e.g. reading byte wide values from 16bit data bus (here, UB and LB control comes handy). I think this is not very good explained in STR9 documentation and I would ask STM to update EMI section in their datasheet and usermanual with detailed information on vaious contolling and access.

[kais]

Posted on May 17, 2011 at 09:30Hi honeyman, Additional Signals including ready signal will be available in the LFBGA package. Specification related to this item will be provided in the next data sheet release.

[stefano239955_stm1_stmicro]

Posted on May 17, 2011 at 09:30

for WR signal if you need it you can use a logic and of WRL & WRH :)

the upper and lowe write are for byte access in 16bit wide data bus. To connect a 16bit SRAM I used the 16bit mux EBI. I connected the 16 bits to the device data, I used a couple of hc573 to demux the address a0-a16 using EMI_ALE as latch enable. a 32bit access is performed as 2 16 bit access.

[spurious]

Posted on May 17, 2011 at 09:30

stevejamal:

hm... somehow you just repeated what is written in user manual or datasheet. Let's assume that I want to connect EMI to 16bit wide SRAM such as BS616LV2011. I still can't see how is WRL and WRH (that are used only when writting data to SRAM) can be used for byte access when reading data. It is not possible to control UB and LB when reading data with signals that change only in writting phase. So, it seems that besides muxed data/address bus additional logic is also required for WR signal. And I think that you have to use logic OR with WRH and WRL. As I can see, no byte access control (UB and LB) is possible when reading from external SRAM. I still haven't got my STR9 board to check this and I'd like to develop external memory add-on board ASAP. Can someone else (if not STM) check this and clearify once for all. And what happens if byte-aligned access is required (both read and write)? :|

[stefano239955_stm1_stmicro]

Posted on May 17, 2011 at 09:30

sorry! I misandestud your question :) !

WRL and WRH are used to write the byte, not to read! To read a 8/16 bit data you have to use the EMI_RD. in general the processor manage the word in order to give you the desidered byte. I made a couple of test to be sure... when you read a 8 bit wide data you always perform a 16 bit wide read.