Enable performance monitor

David Dieckow · ‎2017-12-05

Posted on December 05, 2017 at 14:04

Hi,

I'm trying to enable performance monitor on SPC58x series without luck so far. I tried the following:

e_lis %r3, 0x8000

e_or2i %r3, 0x0000

mtpmr 400, %r3 # freeze all global counters

e_lis %r3, 0x27

e_or2i %r3, 0x0000 #event 39

mtpmr 144, %r3 #set up pipeline stall event in counter 0

e_lis %r3, 0x39

e_or2i %r3, 0x0000 #event 57

mtpmr 145, %r3 #set up data cache line fills event in counter 1

e_lis %r3, 0x0

e_or2i %r3, 0x0

mtpmr 400, %r3 # un-freeze all global counters

But the counter register (PMCx) do not increase at all. What am I missing?

Thank's, David

Erwan YVIN · ‎2017-12-06

Posted on December 06, 2017 at 11:10

Hello David ,

There is a useful document from NXP Side.

it is the same core. There are some slides how to setup the PMR.

https://community.nxp.com/docs/DOC-105754

Best regards

Erwan

David Dieckow · ‎2017-12-06

Posted on December 06, 2017 at 11:27

Hi Ewan,

thank's that might help, I will try. (Actually this document is from Freescale, STM does not provide much information on how to enable and use performance monitors, the datasheet is not very helpful).

I also used

https://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwi0r97mlfXXAhVEPFAKHbEcB3IQFggqMAA&url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fapplication-note%2FAN4341.pdf&usg=AOvVaw2TKmrmcTThhV7SKlHvZ2lI

document from NXP that explains how performance monitor can be used, thats were I got the sample code from. The register structure is a little bit different between NXP and STM perfomance monitor but I already adapted this to STM register structure. I also read somethimg about SPU but don't know what I should to with it to enable the performance monitor.

Regards,

David

Erwan YVIN · ‎2017-12-07

Posted on December 07, 2017 at 09:23

Hello David ,

In Autosar part and SOC functional Valid part, they do not use PMR.

I think that in Autosar part, they use SPU chapter Sequence Processing Unit (SPU)

I am asking an application note about SPU.

Best regards

Erwan

David Dieckow · ‎2017-12-07

Posted on December 07, 2017 at 09:38

Hi Erwan,

I don't use Autosar but bare-metal OS. I don't understand how PMR and SPU do work together or are they independent?

Regards,

David

David Dieckow · ‎2017-12-11

Posted on December 11, 2017 at 08:12

Dear Erwan,

sorry, but the document does not really help. Still the performance monitor is not counting.

Do you have any other suggestions I might look into?

Thank's and regards,

David

Erwan YVIN · ‎2017-12-11

Posted on December 11, 2017 at 10:09

Hello David ,

After investigation cf Chap 13 Debug and Trace and Chap 64 RM0407

Soc Functional valid team are using cmm script (Trace32) to enable the SPU

(cf SPU_SE Table 1445)

Best regards

Erwan

David Dieckow · ‎2017-12-11

Posted on December 11, 2017 at 10:25

Dear Erwan,

I cannot find RM0407 can you provide a link?

Also I don't use Trace32 for debugging but UDE STK (latest version 4.8.6). Nervertheless, can you provide the CMM-Script or tell me how I can do the same with UDE STK (or at least how to activate it by code).

So my assumption is correct that SPU needs to be configured to activate performance monitor?

Regards,

David

Erwan YVIN · ‎2017-12-11

Posted on December 11, 2017 at 10:35

Hello David ,

could you give me your MCU used ?

because the RM should be given by an other way. (by marketing way or field application engineer)

Best regards

Erwan