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SPC58xC.h SEMA42_tag structure

kb24
Senior

Hello, there may be mistake in ST library. In reference manual registers are like that.0693W00000LyDMdQAN.png0693W00000LyDN2QAN.pngIn the library SEMA4_RSTGT has two different addresses for read and write but those are in the same address.

0693W00000LyDOeQAN.png0693W00000LyDNgQAN.pngWith this when I try to reset gate it goes to one of error handlers, if I comment out RSTGT_W I can reset gates without any problem.

1 ACCEPTED SOLUTION

Accepted Solutions
ODOUV.1
ST Employee

Hello,

you are right this is an error in definition.

You can use this new definition instead of:

/**************************************************************************/

/*         Module: SEMA42      */

/**************************************************************************/

struct SEMA42_tag {

  union {

    vuint8_t R;

    struct {

      vuint8_t unused_0:4;

      vuint8_t GTFSM:4;

    } B;

  } GATE[16];

  vuint8_t ADR_reserved0[48];

  union {

    vuint16_t R;

    struct {

      vuint16_t RSTGDP:8;

      vuint16_t RSTGTN:8;

    } B;

    struct {

      vuint16_t unused_0:2;

      vuint16_t RSTGSM:2;

      vuint16_t RSTGMS:4;

      vuint16_t RSTGTN:8;

    } B_read;

  } RSTGT_W;

#define RSTGT_R RSTGT_W

};

Thank you for this report.

Best regards,

-Olivier

View solution in original post

1 REPLY 1
ODOUV.1
ST Employee

Hello,

you are right this is an error in definition.

You can use this new definition instead of:

/**************************************************************************/

/*         Module: SEMA42      */

/**************************************************************************/

struct SEMA42_tag {

  union {

    vuint8_t R;

    struct {

      vuint8_t unused_0:4;

      vuint8_t GTFSM:4;

    } B;

  } GATE[16];

  vuint8_t ADR_reserved0[48];

  union {

    vuint16_t R;

    struct {

      vuint16_t RSTGDP:8;

      vuint16_t RSTGTN:8;

    } B;

    struct {

      vuint16_t unused_0:2;

      vuint16_t RSTGSM:2;

      vuint16_t RSTGMS:4;

      vuint16_t RSTGTN:8;

    } B_read;

  } RSTGT_W;

#define RSTGT_R RSTGT_W

};

Thank you for this report.

Best regards,

-Olivier