We are using the IIS3DWB eval board and noticed that occasionally the values in at least one of the output registers are double what they should be while the accelerometer is at rest in 8g mode. This happens with BDU on and even when the status flag is checked before retrieving data and when reading from the FIFO. example of output data:
----------------------
|At 1673363677710ms
|X: 4 |Y: -9 |Z: -15
|resulting vector: 17
----------------------
|At 1673363677760ms
|X: 4 |Y: -5 |Z: -15
|resulting vector: 16
----------------------
|At 1673363677811ms
|X: 4 |Y: -7 |Z: -16
|resulting vector: 17
----------------------
|At 1673363677862ms
|X: 4 |Y: -4 |Z: -16
|resulting vector: 16
----------------------
|At 1673363677913ms
|X: 4 |Y: -4 |Z: -16
|resulting vector: 16
----------------------
|At 1673363677963ms
|X: 4 |Y: -4 |Z: -15
|resulting vector: 16
----------------------
|At 1673363678014ms
|X: 4 |Y: -4 |Z: -15
|resulting vector: 16
----------------------
|At 1673363678065ms
|X: 4 |Y: -6 |Z: -30
|resulting vector: 30
With no movement the OUTZ_H_A register doubles, this has been observed in every register at different times/orientations of the accelerometer. Below is the init sequence in C++
#define IIS3DWB_CTRL1_XL 0x10
#define IIS3DWB_FIFO_CTRL4 0x0A
#define IIS3DWB_CTRL8_XL 0x17
#define IIS3DWB_CTRL3_C 0x12
#define IIS3DWB_STATUS_REG 0x9E
#define IIS3DWB_OUTX_H_XL 0xA9
#define IIS3DWB_OUTY_H_XL 0xAB
#define IIS3DWB_OUTZ_H_XL 0xAD
#define powerDown 0x0C
#define startUp 0xAC
#define fifoOff 0x00
#define lowPass 0x00
#define BDUenable 0x44
#define sw_reset 0x01
. . .
//initial startup 10Mhz SPI mode 3
result = lgSpiOpen(0, 0, 10000000, 3);
usleep(10000);
//reset software
txBuffer[0] = IIS3DWB_CTRL3_C;
txBuffer[1] = sw_reset;
fd = lgSpiWrite(result, txBuffer, 2);
//power down accel
txBuffer[0] = IIS3DWB_CTRL1_XL;
txBuffer[1] = powerDown;
fd = lgSpiWrite(result, txBuffer, 2);
//shut fifo off
txBuffer[0] = IIS3DWB_FIFO_CTRL4;
txBuffer[1] = fifoOff;
fd = lgSpiWrite(result, txBuffer, 2);
//enable lowpass filter 6.3khz
txBuffer[0] = IIS3DWB_CTRL8_XL;
txBuffer[1] = lowPass;
fd = lgSpiWrite(result, txBuffer, 2);
//enableBDU
txBuffer[0] = IIS3DWB_CTRL3_C;
txBuffer[1] = BDUenable;
fd = lgSpiWrite(result, txBuffer, 2);
//start back up with +/-8g mode, all other defaults
txBuffer[0] = IIS3DWB_CTRL1_XL;
txBuffer[1] = startUp;
fd = lgSpiWrite(result, txBuffer, 2);
and the init sequence when trying with the fifo:
//reset software
txBuffer[0] = IIS3DWB_CTRL3_C;
txBuffer[1] = sw_reset;
fd = lgSpiWrite(result, txBuffer, 2);
//power down accel
txBuffer[0] = IIS3DWB_CTRL1_XL;
txBuffer[1] = powerDown;
fd = lgSpiWrite(result, txBuffer, 2);
//shut fifo off
txBuffer[0] = IIS3DWB_FIFO_CTRL4;
txBuffer[1] = fifoOff;
fd = lgSpiWrite(result, txBuffer, 2);
//enable fifo in continous mode
txBuffer[0] = IIS3DWB_FIFO_CTRL4;
txBuffer[1] = continuousMode;
fd = lgSpiWrite(result, txBuffer, 2);
//set data rate for fifo
txBuffer[0] = IIS3DWB_FIFO_CTRL3;
txBuffer[1] = batchDataRate;
fd = lgSpiWrite(result, txBuffer, 2);
//set watermark to 1
txBuffer[0] = IIS3DWB_FIFO_CTRL1;
txBuffer[1] = watermark1;
fd = lgSpiWrite(result, txBuffer, 2);
//set fifo depth to watermark
txBuffer[0] = IIS3DWB_FIFO_CTRL2;
txBuffer[1] = watermark2;
fd = lgSpiWrite(result, txBuffer, 2);
//enable lowpass filter 6.3khz
txBuffer[0] = IIS3DWB_CTRL8_XL;
txBuffer[1] = lowPass;
fd = lgSpiWrite(result, txBuffer, 2);
//start back up with +/-8g mode, all other defaults
txBuffer[0] = IIS3DWB_CTRL1_XL;
txBuffer[1] = startUp;
fd = lgSpiWrite(result, txBuffer, 2);
