STM32 MPUs

OpenSTLinux: Starter Package, plain image (FlashLayout_sdcard_stm32mp257f-dk-optee.tsv), version 5.0.17-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10M33 firmware: Zephyr RTOS (4.4.99), board target stm32mp257f_dk/stm32mp257fxx/m33, loaded and started from Linux via remoteproc.Goal: Drive a SPI device (Qorvo DW3000) from the Cortex-M33 over SPI6, which is exposed on the CN5 header (GPIO10/SPI6_MOSI = PC7, GPIO9/SPI6_MISO = PC4, GPIO11/SPI6_SCK = PF7).When the M33 firmware performs a SPI transfer, the GPIO chip-select line toggles correctly (verified on a logic analyzer), but SCK never produces any clock pulses & the line stays flat. Consequently no data is exchanged (MOSI/MISO flat). The transfer call itself returns; it just produces no clock.What I have already checked:-RIFSC firewall: SPI6 shows as NSEC, NPRIV, CID filtering disabled (from the RIFSC debug dump) — i.e. not blocked/assigned exclusively to the A35.-Clocks: clk_summary shows both ck_icn_p_spi6 (~200 MHz) and ck_ker_sp

 I am working with an STM32MP257F-EV1 Evaluation board (board reference MB1936, target STM32MP257FAI3) and am unable to debug the Cortex-M33 core independently over SWD. Setup:- Board: STM32MP257F-EV1- Tools: STM32CubeIDE and STM32CubeProgrammer.- Boot switches (SW1) set to Development boot: Boot0=1, Boot1=1, Boot2=0, Boot3=0- JP3: no jumper fitted (STLINK-V3EC active)- CubeIDE debug configuration: Load Mode = "thru JTAG/SWD link (Engineering mode)", Access port = "8 - Cortex-M33", SWD interfacei have attached debug error screenshot. i want to debug a standalone (bare-metal) application running on the Cortex-M33 over SWD.Could you help with the following:Is it possible to debug the Cortex-M33 via SWD/JTAG on the STM32MP257F-EV1 without booting from SD card, eMMC, or QSPI. What is the recommended/supported procedure for attaching a debugger (SWD) to the M33 core when running a standalone bare-metal application. Are there specific boot configuration or provisioning steps required (e.g.,

Hello,I'm working with an STM32MP257 and encountering unexpected behavior regarding RTC resource isolation between the Cortex-M33 (bare metal/HAL) and Cortex-A35 (OpenSTLinux).I performed a simple test where my Cortex-M33 requests the initialization resource using the Resource Manager and holds it while reading the time registers:ResMgr_Status_t st = ResMgr_Request(RESMGR_RESOURCE_RIF_RTC, RESMGR_RTC_INIT_RSC);if (st == RESMGR_STATUS_ACCESS_OK){// Reading registers directly while holding the lockuint32_t tr = RTC->TR; uint32_t dr = RTC->DR;// ... intentionally omitting ResMgr_Release to test the lock ...} While the M33 is actively holding this RESMGR_RTC_INIT_RSC lock, I execute the following command from the Linux shell on the A35 core:hwclock --set --date="2026-07-18 12:34:56" --utcTo my surprise, the time is successfully changed.My question is: why does this happen? Does the OpenSTLinux RTC driver (rtc-stm32.c) completely bypass the RIF synchronization mechanism and force its

On the STM32MP257F-EV1 evaluation board, configuring SPI3 in slave mode (spi-slave;) works correctly for the SCK, MOSI, and MISO signals, but the NSS (chip select) pin — PB1, using the documented-correct AF1 alternate function — silently fails to be claimed by the pin controller. No error or warning is logged anywhere. All three other SPI3 pins on the same bus, using the same AF1 value, claim successfully.

Hi Is TouchGFX supported on MP1 or MP2 boards ?I found this article : https://wiki.st.com/stm32mpu/wiki/How_to_install_X-TouchGFX_MPU_AddonBut it looks like its only 1 board

How to flash M4 Core in STM32MP157F-DK2 using STM32Cube Programmer..? I have the Hex file but whenever I open Cube Programmer ST-LINK is not Detecting instead its Deteccting as USB, and in Device manager USB is recognized as STM32 Bootloader

I have a working RLT8211F at my STM32MP257F board.I wonder why only the hardware reset is working PYRSTB (pin 12), but the software reset won't work?Should they not do the exactly the same thing?My Ethernet PHY is working, but it seems it requires as hardware reset GPIO from the MPU.I have tried to modify the code in realtek.c and phy_device.c by adding the function genphy_soft_reset to the struct in realtek.c. }, {  PHY_ID_MATCH_EXACT(0x001cc916),  .name = "RTL8211F Gigabit Ethernet",  .probe = rtl8211f_probe,                .soft_reset = genphy_soft_reset, /* <------- this */  .config_init = &rtl8211f_config_init,  .read_status = rtlgen_read_status,  .config_intr = &rtl8211f_config_intr,  .handle_interrupt = rtl8211f_handle_interrupt,  .set_wol = rtl8211f_set_wol,  .get_wol = rtl8211f_get_wol,  .suspend = rtl8211f_suspend,  .resume = rtl8211f_resume,  .read_page = rtl821x_read_page,  .write_page = rtl821x_write_page,  .flags = PHY_ALWAYS_CALL_SUSPEND,  .led_hw_is_supported

I am trying to increase the cpu speed of a custom board with stm32h743VIT6 and 16mhz crystal. However, once I change the speed, the UART output prints out gibberish. I have verified the UART works with the HSI at default speed of 64Mhz. Attached is the code and board schematics. Thanks for the help. 

Hello,We are designing a custom board using the STM32MP157FAC1 and have used the STPMIC1APQR PMIC to power the microprocessor, similar to the STM32MP157F-DK2 evaluation board.We need to provide a Power LED on the front panel of the card to indicate that all the power rails generated by the STPMIC1APQR are operating correctly.Since the STPMIC1APQR does not provide a dedicated Power_Good (PGOOD) output signal, we are considering using the RSTn pin (Pin 1) to drive the Power LED along with its connection with NRST pin of STM32MP157FAC1. Our understanding is that RSTn is released (driven high) only after the power-up sequence has completed successfully and all required power rails are within specification. If any monitored power rail fails, RSTn would be asserted low.We plan to use a transistor stage to drive the LED from the **RSTn** signal so that:(1.) RSTn = High: Power LED ON(2.) RSTn = Low: Power LED OFFCould you please confirm whether this is approach is okay or not ? If not, kindly

After upgrading MX to 6.18.0 when I run STM32CubIDE 1.19 it crashes when doing it’s upgrade check.As it happens so fast I can’t actually see what is happening but managed to open the Preferences to set the Firmware Updater to Off Line Mode..I am using 1.19 as I prefer the MX integration in CubeIDE. So be warned ;)  

Hello, I have a TFT LCD display that uses a ST7789v controller. I would like to interface with it using the KMS DRM subsystem in Linux. I have been having issues getting this to work though.So far I have confirmed that the default driver to ST7789v controllers is running, but it only seems to create a drm_panel. I am having trouble creating/linking it to a connector/CRTC/encoder. I have any DBI related options enabled in menuconfig, but I don’t see any way to interface with DBI displays when running modetest. Does anyone have any advice as to what I need to do to get DRM working with this display? Will I need to write my own drivers? I can provide any existing code/devicetree configurations if need be.

I  have already submitted the case in ST Online Support, but have had no reply for over two weeks.

Hello,I’m using an Karo SOM module (MP257) on a custom board with SFP module.The SFP module is powered with the main 3.3V regulator. It has a TX_DISABLE input (0=ON, 1=OFF). This input :Is TTL Has an internal pull-up R (around 10k) Has an external pull-down R (10k) In connected to PE2This makes a voltage divider : without driving the TX_DISABLE line, the voltage is something like 3.3V / 2 (1.8V to be precise)Some simple tests to confirm that :SFP module unplugged => voltage is driven only by the pull down R => 0V A source meter on the TX_DISABLE confirms the presence and value of the internal RPU. Now let’s play with the MP2. Is this processor able to blink a led ? Don’t laugh, nothing could be further from the truth. After linux boot : gpioinfo shows PE2 is input. It should logically be driven by the driver, but for an obscure reason, this is not the case. At least we can do things manually… Set it to 0 ?gpioset -b disabled -d push-pull PE2=0=> Voltage is still 1.8V Ok, bad.

Hi ST team,I am working with an STM32MP257 where Linux runs on the Cortex-A35 and a FreeRTOS application runs on the Cortex-M33. The M33 firmware is loaded and started by Linux using remoteproc.The application is running correctly, but I would like to understand the recommended workflow for debugging the M33 application.I have read the "Debug support" section of RM0457 and understand that the M33 can be accessed through the shared SWD/JTAG interface by selecting the appropriate Access Port. However, I'm still not clear on the recommended debug workflow when the M33 is managed by remoteproc.My questions are:Can STM32CubeIDE/ST-LINK attach to an already running M33 started by remoteproc, or should the M33 be stopped first? If Linux has already loaded the firmware, should the debugger load only the ELF symbols instead of downloading the application again? Is there any special OpenOCD/ST-LINK or CubeIDE configuration required for this use case? Is there an ST application note or example de

Hello,In the reference schematic of the STM32MP157F-DK2, the HSE clock is generated using the NDK NZ2016SH 24 MHz END4869F oscillator. However, this part is not readily available, and we are therefore looking for a suitable alternative.Could you please confirm whether the Abracon’s part ASE-24.000MHZ-LR-T can be used as a replacement to provide the HSE clock for the STM32MP157FAC1 device ? If this part is not recommended, kindly suggest a suitable alternative that is compatible with the STM32MP157FAC1.Regards

Hello,We are designing a custom board using the STM32MP157FAC1 device. In our design, we are not using the DSI interface or the ADC peripheral.We would like your guidance on the recommended handling of the corresponding unused pins.(1.) DSI Interface:Since the DSI interface is not used, how should the following differential signals be terminated ?(a.) DSI_CKP / DSI_CKN(b.) DSI_D0P / DSI_D0N(c.) DSI_D1P / DSI_D1N(2.) Analog Inputs:As the ADC is not being used, what is the recommended way to connect or terminate the ANA0 and ANA1 pins ?Could you please advise the recommended hardware implementation for these unused pins?Regards,

Hi,I'm bringing up Ethernet (RGMII) on a custom STM32MP257 board using a Marvell 88E1512 PHY.The MAC driver loads successfully, the PHY is detected, but bringing the interface up fails with a timeout.I have attached the driver code, dts and pinctrl.dtsi for you reference. eth1_mdio_pins_mx: eth1_mdio_mx-0 {pins1 {pinmux = <STM32_PINMUX('A', 9, AF10)>; /* ETH1_MDC */bias-disable;drive-push-pull;slew-rate = <2>;st,io-clk-edge = <0>;st,io-retime = <0>;st,io-delay-path = <0>;st,io-delay = <0>;};pins2 {pinmux = <STM32_PINMUX('A', 10, AF10)>; /* ETH1_MDIO */bias-disable;drive-push-pull;slew-rate = <0>;st,io-clk-edge = <0>;st,io-retime = <0>;st,io-delay-path = <0>;st,io-delay = <0>;};};eth1_mdio_sleep_pins_mx: eth1_mdio_sleep_mx-0 {pins {pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* ETH1_MDC */<STM32_PINMUX('A', 10, ANALOG)>; /* ETH1_MDIO */};}; eth1_rgmii_pins_b: eth1-rgmii-1 {pins1 {pinmux = <STM32_PINMUX('

Hi community,I am using yocto build ( version - openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11) in this I am facing challenge over below build time error.Exception: subprocess.CalledProcessError: Command 'tar --exclude=./sysroot-only -cf - -C .../linux-libc-headers/6.6/image -p -S . | tar -xf - -C .../linux-libc-headers/6.6/package' returned non-zero exit status 2. got *at() syscall for unknown directory, fd 4 unknown base path for fd 4, path include couldn't allocate absolute path for 'include'. function package_prepare_pkgdata finished DEBUG: Executing python function perform_packagecopy ERROR: Error executing a python function in exec_func_python() autogenerated:The stack trace of python calls that resulted in this exception/failure was: File: 'exec_func_python() autogenerated', lineno: 2, function: <module> 0001: *** 0002:perform_packagecopy(d) 0003: File: '/home/datadir/EVK-build-CMS/layers/openembedded-core/meta/classes-global/package.bbclass', lineno: 363, function: perform

I have a custom design with STM32mp135f + MT41K256M16TW-107 DDR3L @ 533MHz that I want to bring up. I built a Linux image based on OpenSTLinux guides and it boots until my kernel is loaded (uboot logs : “starting kernel”) then its crashes without any logs even with earlycon. By testing the DDR with ST DDR Tool, I realized that byte-masked writes fail (test 9), but halfword & RMW32 work.  I noticed the byte lane swap but it is identical on the dk board. I am a bit lost and don’t know if the issue is timing/config related or due to my hardware design.  

Hello,We are designing a custom board using the STM32MP157FAC1 device. For programming and debugging, we are providing an STDC14 connector on our board and use the STLINK-V3SET debugger/programmer.As per AN5031 (Section 8.3.3), the recommended ESD protection device is ESDALC6V1W5. Snapshot is attached for kind reference.We have the following queries:Query 1:Can we use the HSP053-4M5 device instead of the ESDALC6V1W5 for ESD protection? We are already using the HSP053-4M5 to protect the data, clock, and command lines of the microSD card interface. Using the same device for the STDC14 interface would help us optimize the BOM.Query 2:Can we connect USART1_TX (PA9) and USART1_RX (PB15) of the STM32MP157FAC1 to Pin 14 (T_VCP_TX) and Pin 13 (T_VCP_RX), respectively, on the STDC14 connector for the STLINK-V3SET Virtual COM Port interface? Regards,PS  

Hi ST Team,I am facing an issue while building an OpenSTLinux project for STM32MP255.EnvironmentBoard: STM32MP255 OpenSTLinux: 5.0.8 Yocto Distribution: openstlinux-weston Ubuntu: 22.04 LTS Kernel: 6.8.0-124-generic pseudo version: 1.9.0+git pseudo SRCREV: 28dcefb809ce95db997811b5662f0b893b9923e0  ProblemThe build fails during:build-info-openstlinux.bb:do_packageThe failure occurs inside Yocto's standard perform_packagecopy() while executing:tar --exclude=./sysroot-only \-cf - \-C image \-p -S . |tar -xf - \-C packageThe error is:got *at() syscall for unknown directory, fd 4unknown base path for fd 4, path buildcouldn't allocate absolute path for 'build'tar: ./etc/build: Cannot open: Bad addresstar: Exiting with failure status due to previous errors Investigation PerformedI verified the following:1. RecipeThe build-info-openstlinux.bb recipe is unchanged and only creates the /etc directory.The /etc/build file is generated by image-buildinfo.bbclass.2. Generated fileVerified that:ima

I have a custom board using STM32MP131D integrated with ethernet PHY TI DP83867CR. I am using RGMII interface with a Magjack RJ45.I have been benchmarking the ethernet performance at 100Mbps using iperf3 with the custom board as the iperf client and my Linux test PC as the iperf server.When I run iperf in client mode on the custom board (DUT) in TCP, I see really bad TX performance:root@stm32mp131-sga:~# iperf3 -c 10.10.14.200Connecting to host 10.10.14.200, port 5201[ 5] local 10.10.14.102 port 35028 connected to 10.10.14.200 port 5201[ ID] Interval Transfer Bitrate Retr Cwnd[ 5] 0.00-1.00 sec 0.00 Bytes 0.00 bits/sec 3 1.41 KBytes[ 5] 1.00-2.00 sec 0.00 Bytes 0.00 bits/sec 2 1.41 KBytes[ 5] 2.00-3.00 sec 0.00 Bytes 0.00 bits/sec 1 1.41 KBytes[ 5] 3.00-4.00 sec 0.00 Bytes 0.00 bits/sec 1 1.41 KBytes[ 5] 4.00-5.00 sec 0.00 Bytes 0.00 bits/sec 1 1.41 KBytes[ 5] 5.00-6.00 sec 0.00 Bytes 0.00 bits/s

WebKit is now releasing a new upgrade for their WPE WebKit API so the web browser can run on the GPU instead of CPU.Here is what the WPE WebKit Dev Team is writing:In any case, try the new WPEPlatform API (https://wpewebkit.org/) instead of Cog, and that suggestion still stands. Cog is currently at the end of its lifetime and won't see more stable versions, as we are fully focused on this new API that will not only make integration much simpler but will also allow making the most of more modern features like dmabuf, which enables zero-copy buffer sharing both at the graphics and multimedia layers of WPE, therefore increasing performance, stability and smoothness.Now, while the new WPEPlatform API will be released as stable in September, it's still fairly mature and you can already try it out with ToT or with the latest unstable releases, as well with the latest stable release (2.52.3). See some links to the API docs below:https://wpewebkit.org/reference/unstablehttps://wpewebkit.org/re

Both Micron and Samsung are putting LPDDR4 memories to EOF.What is the guaranty that STM32MP2 can support other affordable memories e.g LPDDR5?

Factory flashing of the STM32MP135 will be part of some device testing (probably ICT) during production at an external manufacturer. So, SSP will play a part in this. Testing and flashing the device will be automated as much as possible with a custom app (GUI or CLI) running on a PC. This app will execute STM32CubeProgrammer_CLI with corresponding arguments in the background.As I understand it, once the whole SSP process has finished, it cannot be done on the same device again. I need a way to test the automation app numerous times before giving the whole package to the manufacturer. I didn't find a clear solution to this, and I don't want to buy many STM32MP135 development boards or HSM cards for it. For the HSM part: I read in the forum that the licence file can be extracted from the smart card and then use it with the STM32CubeProgrammer but I'm not 100% sure about that.So, my questions are:What is the recommended way to test flashing with SSP on a single device? Can a licence file