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Srikanth1
Associate III
August 20, 2026
Question

Intermittent TXUNDERR on SDMMC1 eMMC write — only after cold boot, only on write (not read)

  • August 20, 2026
  • 0 replies
  • 30 views

 

Setup

  • STM32MP157, Cortex-A7, bare-metal
  • SDMMC1 → eMMC (61071360 blocks, 512B), CardType 1
  • Kernel clock: pll4_p_ck (125MHz) via RCC_SDMMC12CKSELR
  • IDMA: single-buffer mode
  • Test: single-block write (512B) to block 4096, then read-back + compare

 

Problem After a cold power-on, the first HAL_MMC_WriteBlocks_DMA() intermittently fails with TX FIFO underrun. Not every cold boot — boot-to-boot random, same config either way.

On a boot where it fails, it fails on every retry (tested 5x), even with a full peripheral reset (RCC AHB6 reset + reinit) between each attempt — card info (BlockNbr etc.) verified correct every time, so it's not stale driver/card state.

Read never fails, on the same bad boot, same clock, same peripheral.

Register data — same board/config, two different cold boots

Passing boot:

DCOUNT@DataEnd: 0x0, STA@DataEnd: 0x100 → RESULT: PASS

Failing boot (5 attempts, each after full reinit):

Attempt 0: DCOUNT@Err=0x098, STA@Err=0x1010, ErrCode=0x10(TXUNDERR)→0x14 (+CMD timeout on stop)
Attempt 1: DCOUNT@Err=0x178, STA@Err=0x1010, ErrCode=0x10→0x14
Attempt 2: DCOUNT@Err=0x138, STA@Err=0x1010, ErrCode=0x10→0x14
Attempt 3: DCOUNT@Err=0x078, STA@Err=0x1010, ErrCode=0x10→0x14
Attempt 4: DCOUNT@Err=0x178, STA@Err=0x1010, ErrCode=0x10→0x14

STA=0x1010 = TXUNDERR (bit4) + TXFIFOE (bit12). DCOUNT@Err varies each attempt (out of 0x200 total) — not a fixed boundary.

Ruled out

  • Cache coherency (buffers in non-cacheable MMU region)
  • IDMA double-buffer misconfig (already using single-buffer)
  • Stale driver/card state (full reinit verified correct, still fails)
  • Bad card (reproduced on 2 different eMMC chips)
  • General clock instability (read never fails on the same bad boot)

Question Given write fails and read never does on the same boot/clock, is there a known timing-margin difference between SDMMC write vs read DMA on STM32MP157 — e.g. minimum FIFO pre-fill delay before issuing the write command, or a cold-boot/first-DDR-access latency consideration? Has anyone seen write-only underruns tied specifically to cold power-on rather than warm reset?

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