How do I enable ETH Clock Output for RGMII?

[ST Migration account]

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I wonder how I can enable ETH Clock Output for my Realtek RTL8211F Ethernet PHY. Right now, the crystal for RTL8211F won't start and I don't know why. I'm guessing that it's an unstable crystal. Anyway! To enable the ETH Clock Output for my Ethernet PHY, I've set the the ETH Clock Output:

Then I've set the CK_KER_ETH1 to either 25 MHz or 125 MHz. I've chosen the 25 MHz option.

According to the STM32MP257F reference manual RM0457, the ETH Clock Output can only be used for 125 MHz.

But according to the STM32MPU Wiki, it's possible to use 25 MHz as ETH Clock Output:

https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_25_MHz_on_ETH_CLK_-28no_PHY_Crystal-29--CLK125_from_PHY_-28Reference_clock_-28standard_RGMII_clock_name-29-29

All you need to do Is to add the pinmux

eth1_clk_pins_mx: eth1_clk_mx-0 {
pins {
pinmux = <STM32_PINMUX('F', 3, AF9)>; /* ETH1_CLK */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
eth1_clk_sleep_pins_mx: eth1_clk_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('F', 3, ANALOG)>; /* ETH1_CLK */
};
};

Select the rgmii or rgmii-id option and use the max speed option. 

&eth1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth1_clk_pins_mx>, <&eth1_mdio_pins_mx>, <&eth1_rgmii_pins_mx>;
pinctrl-1 = <&eth1_clk_sleep_pins_mx>, <&eth1_mdio_sleep_pins_mx>, <&eth1_rgmii_sleep_pins_mx>;
status = "okay";
/* USER CODE BEGIN eth1 */
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy1_eth1>;
mdio1{
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1_eth1:ethernet-phy@1{
compatible = "ethernet-phy-id001c.c916";
/* No Reset pins */
realtek,eee-disable;
reg = <1>;
};
};
/* USER CODE END eth1 */ };

According to my PLL6 in op-tee:

pll6:st,pll-6 {
st,pll = <&pll6_cfg_400MHz>;
pll6_cfg_400MHz: pll6-cfg-400MHz{
cfg = <50 1 1 3>;
src=<MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>;
};
/* USER CODE BEGIN pll6 */
/* USER CODE END pll6 */
};

Question:

What part of the configuration says that ETH1_CLK is going to provide the Ethernet PHY with a 25 MHz clock in RGMII mode?

By looking inside the linux code, I can definitely see that using the ck_ker_eth1 = 25 MHz in STM32CubeMX, will enable the eth_ck = true for DWMAC. Is that a guarantee that ETH1_CLK will provite the Ethernet PHY with 25 MHz?

case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
val = SYSCFG_ETHCR_ETH_SEL_RGMII;
if (clk_rate == ETH_CK_F_25M)
dwmac->enable_eth_ck = true;
if ((clk_rate == ETH_CK_F_125M) &&
(dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
dwmac->enable_eth_ck = true;
val |= SYSCFG_ETHCR_ETH_CLK_SEL;
}
dev_dbg(dwmac->dev, "SYSCFG init : PHY_INTERFACE_MODE_RGMIIn");
break;

https://github.com/STMicroelectronics/linux/blob/80d29586bafa4734bad35a8f063919fdd79f5dec/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c#L291-L304

The reason:

The reason why I'm asking is because according the reference manual, I the ETH1_CLK is the output for the PHY...but where do find the ETH1_DIRECT setting? Is it inside the DT? Or is it hard coded in the linux code?

Yes, I can understand this clock schematic.

As you can see, the ETH1_DIRECT is from the ETHSW register.

 

 

[ST Migration account]

The ETH1_DIRECT is 1 by default when ETHSW is not enabled.

So as long the CK_KER_ETH1 is 25 MHz or 125 MHz, the ETH1_CLK will be an output, else disabled.