STM32 MPUs

Hi everyone,I'm using STM32MP2 OpenSTLinux 6.6 Yocto Scarthgap MPU v24.11.06 with Linux kernel 6.6.48.I am trying to interface a Waveshare LVDS 10.1" FT5x06 touch display with the STM32MP257F-DK. We designed a custom PCB for the required pin mapping. 1. Display :Initially, the display was not working with the original compatible string. After changing the panel compatible to "panel-lvds" only then display started working. panel_lvds: panel-lvds { compatible = "panel-lvds";... /*compatible = "edt,etml0700z9ndha", "panel-lvds";*/ }  2. I2C Touch / HDMI Address :The FT5x06 touch controller uses I2C address 0x38.The ADV7535 HDMI device also uses 0x38 as one of its register-map addresses. Since I am not using HDMI for this test, I changed that ADV7535 address from 0x38 to 0x39:&i2c2 { adv7535: hdmi@3d { compatible = "adi,adv7535"; reg = <0x3d>, <0x3c>, <0x3f>, <0x39>; //<0x38>; } ili2511: ili2511@41 { compatible = "ilitek,ili251x

Can the STM32MP231 simultaneously capture or stream four 2-lane MIPI CSI-2 camera streams through a DS90UB960/TDES960 using VC0–VC3?I have reviewed ST’s documentation on “How to use one or multiple multi-stream MIPI CSI cameras.” But did not get complete clarity on simultaneous capture of four camera streams. The documentation example appears to show routing for up to three streams/channels through the DCMIPP pipes (Dump, Main, and Aux).

Could you please provide information on the DMIPS/MHz performance of the A35 core in the STM32MP23? Is this specified in any documentation?

Hello Team,We are currently developing a custom board based on the STM32MP255 and have encountered a routing challenge.According to the STM32MP255 DDR routing guidelines, the single-ended trace impedance should be 55 Ω. However, after optimizing the PCB stack-up and routing, the closest value we have been able to achieve using the Saturn PCB Toolkit is 70 Ω.Could you please confirm whether this deviation from the recommended impedance is acceptable? Specifically, we would like to understand:Will this impact DDR functionality, signal integrity, or overall system reliability? Is 70 Ω within an acceptable tolerance for the STM32MP255 DDR interface, or would you recommend modifying the PCB stack-up to achieve the target 55 Ω?Your confirmation and guidance will help us proceed with confidence before finalizing the board design.DDR Routing imageMeasuring toolLayer Stack-up 

Hi,I have a SoM based on STM32MP135c (QSMP-1351) and I try to enable the secure boot using STM32_Programmer_CLI (STM32CubeProgrammer v2.22.0)Here is the flash layout file used before updating OTP:#opt  Id   Name  Type  Device Offset Binary-    0x01  fsbl-boot    Binary none  0x0   tf-a-loader.stm32-    0x03  fip-boot    FIP   none  0x0   fip-loader.binI can write PKHTH without any issue:STM32_Programmer_CLI -c port=usb1 -otp write word=0x18 value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x19 value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1a value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1b value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1c value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1d value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1e value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1f value=0x????????When I want to lock device, I use the comm

We are currently evaluating a board design based on the STM32MP253FAK3, and would like to confirm the following regarding the DDR4 memory configuration.[Configuration under consideration]MPU：    STM32MP253FAK3Memory devices：    Two DDR4 8 Gbit x8 devices (1 GByte each), mounted as two separate packagesBus width：    16-bit (Byte0 = device #1, Byte1 = device #2)Rank configuration：    Single rank (CS0 / CKE0 / ODT0 shared by the two devices)Total density：    2 GByte[Questions]1. Support for this topologyIs the "two x8 devices / 16-bit" configuration — that is, forming a 16-bit bus using two x8 devices in separate packages — supported on the STM32MP253FAK3?In AN5724 (Guidelines for DDR memory routing on STM32MP2 MPUs), only the following two configurations are described for DDR4:16-bit interface: one x16 device connected point-to-point (Section 3.4)32-bit interface: two x16 devices connected in a fly-by topology (Section 3.2)We could not find any description of a configuration using x8 dev

Hello Experts,I am working on the STM32MP257F-EV1 board (MB1936 Var1.0 Rev.C-01) and following the official OpenSTDroid provisioning guide. I have successfully used flash-device(STM32CubeProgrammer v2.22.0 ) to flash the full eMMC starter image via DFU mode (FlashLayout_emmc_cm33tdcid.tsv). After that, I switched the boot mode from DFU to eMMC (M33-TD) and pressed USER2 + RESET to enter fastboot mode, as described in the documentation. However, instead of entering fastboot, the board goes into an infinite reboot loop.Observed behavior: Serial console (minicom) shows the following repeated sequence: iac exceptions: [159:128]=0x000001IAC exception ID: 128Ooops...[INF] System reset[INF] Reset reason: System reset (SYSRST) (0x94)[INF] init:pmic@33 STPMIC:20 V1.1[INF] welcome to MCUboot: TF-Mv2.1.3-4-g0a94de886[INF] cpu: STM32MP257FAI Rev.?[INF] board: stm32mp257f eval1[INF] board ID: MB1936 Var1.0 Rev.C-01[INF] dts: stm32mp257f-ev1-cm33tdcid-ostl-emmc-bl2.dts[INF] boot device: sdmmc2[INF]

Hello Every One,Hardware / Software EnvironmentBoard: STM32MP257F-EV1Device: STM32MP257FAIxIDE: STM32CubeIDE v2.0.0 (Windows)Firmware package: STM32Cube FW_MP2 v1.2.0OpenSTLinux version: openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11What I DidFlashed OpenSTLinux image to eMMC using USB DFU with:FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsvFlashing completed successfully.Linux boots correctly and I can log in via UART:root@stm32mp2:~#Created a simple GPIO project for Cortex-M33 using STM32CubeMX and STM32CubeIDE:Selected MCU: STM32MP257FAIx (not board)Selected “M33 Master”Toolchain: STM32CubeIDEProject builds successfully without errorsLinker Memory ConfigurationThe generated linker script places CM33 firmware in DDR memory:NS_VECTOR_TBL : ORIGIN = 0x80100000FLASH : ORIGIN = 0x80100600RAM : ORIGIN = 0x80A00000VIRTIO_SHMEM : ORIGIN = 0x812F8000IPC_SHMEM_1 : ORIGIN = 0x81200000So the CM33 firmware is located in DDR (0x80xxxxxx region).ProblemWhen attempting to debug or download

Dear ST-Community,I was able to run QNX8 on stm32mp257f-dk (see it here: https://github.com/KozhinovAlexander/qnx8-bsp-stm32mp257f-dk)I have following boot-stage setup:#Opt Id Name Type IP Offset Binary- 0x01 fsbl-boot Binary none 0x0 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-programmer-usb.stm32- 0x02 fip-ddr FIP none 0x0 fip/fip-stm32mp257f-dk-ddr-opteemin-programmer-usb.bin- 0x03 fip-boot FIP none 0x0 fip/fip-stm32mp257f-dk-opteemin-programmer-usb.binP 0x04 fsbla1 Binary mmc0 0x00004400 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32P 0x05 fsbla2 Binary mmc0 0x00044400 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32PD 0x06 metadata1 FWU_MDATA mmc0 0x00084400 arm-trusted-firmware/metadata.binPD 0x07 metadata2 FWU_MDATA mmc0 0x000C4400 arm-trusted-firmware/metadata.binP 0x08 fip-a FIP mmc0 0x00104400 fip/fip-stm32mp257f-dk-opteemin-sdcard.binPED 0x09 fip-b FIP mmc0 0x00504400 nonePED 0x0A u-boot-env ENV mmc0 0x00904400 noneP 0x10 bootfs System mmc

 Hi,I am working with the STM32MP257F-EV1 board and would like to debug the Cortex-M33 core using the debugger using ST-LINK.Currently, I am unable to debug the Cortex-M33 core directly and I receive an error during the debug connection. I have attached a screenshot of the debug error for reference.I noticed the following behavior: If I boot the Cortex-A35 core from the SD card and allow Linux to complete its boot process, I can then successfully debug the Cortex-M33 core. However, if I do not boot Linux on the A35 core, I am unable to connect to/debug the M33 core. I would like to know whether the Cortex-M33 on the STM32MP257F-EV1 can be debugged standalone, without booting the Cortex-A35/Linux, similar to debugging the Cortex-M4/M7 on a conventional STM32 MCU such as the STM32H745XI-DISCO.Specifically: Is booting Linux on the Cortex-A35 mandatory before the Cortex-M33 can be debugged? Is there a way to debug the Cortex-M33 standalone immediately after reset/power-up, without boot

Hello,We are designing a custom board using the STM32MP157FAC1 device (361 balls with 0.5 mm pitch).As per AN5031 (Page 50), laser vias with a 100 µm (~4 mil) drill hole diameter and 250 µm (~10 mil) outer pad diameter are recommended for BGA balls located within the 0.5 mm pitch matrix. A snapshot of the relevant section is attached for the reference.We would like to clarify whether a Via-On-Pad strategy can be used instead of laser vias for the BGA balls within the 0.5 mm pitch matrix of STM32MP157FAC1 device.Specifically, can we use a via of 200 µm (~8 mil) drill hole diameter and 400 µm (~16 mil) outer pad diameter as via-on-pad on the STM32MP157FAC1 BGA pads instead of the recommended laser vias ? Kindly confirm whether this approach is acceptable from the CAD layout perspective and whether it can be used in the CAD layout of our design.Regards,PS  

Hello everyone,When using libcamera on the STM32MP257 platform (ATK-DLMP257B development board with IMX335 sensor), the DCMIPP driver fails to queue stats buffers to /dev/video4, returning -EINVAL. This causes libcamera to crash with an assertion failure during stream shutdown.Additionally, the DCMIPP post-processor (dcmipp_main_postproc) refuses all YUV format configurations (NV12, YU12, YUV420, etc.), returning Invalid argument (22) for each attempt. The hardware only accepts RGB888/RGB565 output formats.When using libcamera on STM32MP257 platform with IMX335 sensor, the DCMIPP driver fails to queue stats buffers to `/dev/video4`, returning `-EINVAL`. This causes libcamera to crash with an assertion failure (`cache_->isEmpty()`) during stream shutdown.Linux kernel version is 6.6.48.libcamera version is v0.3.0+dirty.Steps to ReproduceBasic libcamera capture with fakesinkgst-launch-1.0 -v libcamerasrc ! \ video/x-raw,format=NV12,width=1920,height=1080,framerate=30/1 ! \ fakesi

Board: STM32MP257F-EV1Image: FLASH-stm32mp2-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10Kernel: Linux 6.6.129USB port: CN15 (USB_DRD, Type-C)I'm trying to run a USB gadget (UVC, via configfs/libcomposite) on CN15, andthe UDC never attaches, even though every layer up to dwc3's pullup steplooks correct:- Type-C/UCSI (M33 firmware USBPD_DRP_UCSI_CM33_NonSecure_stripped.elf,  ucsi-stm32g0-i2c driver) correctly negotiates the port as UFP/device:  /sys/class/typec/port0/data_role = host [device]  /sys/class/typec/port0/power_role = source [sink]  A partner is detected, and the UCSI power-supply object confirms VBUS at  5V. This all live-updates correctly on physical cable unplug/replug.- dwc3 correctly switches to device mode:  /sys/kernel/debug/usb/48300000.usb/mode → "device"- But the pullup never actually happens:  /sys/class/udc/48300000.usb/state stays "not attached" indefinitelyManually retrying via soft_connect just logs "UDC had already started" —the UDC core believes the connect s

I am developing an M33 application on STM32MP257F MPU, I would like to know the steps to import, build and debug secure project for Cortex-M33 in STM32CubeIDE for M33-TD flavor. I would appreciate if any one could tell the best and easy way to deploy custom M33 firmware in to this MPU and test it with or without linux?FYI, I am using STM32MP257F-DK (Discovery Kit) Board. Thanks in advance,Gupta

Hello,  I’m trying to learn how to use the STM32MP135CAEx for a upcomming project.I have been looking online through tutorials and documentation but have a few questions.Project background:I need a device that has 2 ethernet interfaces, a LCD interface and a bunch of common peripherals.I’m a big fan of STM23 controllers and have a few years of experience with them so trying out the MP series would be a next logical step for me.1)My idea was to make a small linux image on run it on the MPU. That linux then should have access to a display with toutch.The display I had in mind is 400x800 pixels.I don’t know if you can run without DDR memory, I’m gone need it, when I look at the standards RAM available.But can you run without?2)Is there a “bring up guide”?I have been trying to set up my ioc but I keep having an error marker in my DDR tab.So I can have a indication of that I understood things correctly. 3)What I’m used to from the controllers is that one a peripheral is configured correctly

Dear ST teamWhy does ST team add the “negedge” flag in DT  for the SDCARD timing initialization on ST eval DKs?Sébastien

I am writing this to help.I have just received my EVB STM32MP257F-DK.When I have connected my USB cable in "USB PWR STLNK".LD5 and LD6 were RED,  LD11 was flashing GREEN once.Installed the SD card and nothing, no boot ?Win11 was claiming that the driver is fine and the latest.The USB port were displayed as regular: USB PORT COM9 and COM10.Pressing the RESET button B1 nothing: No BOOT, no bad character on both ports ???Disconnecting the USB cable was well detected by Tera Term but nothing else.I have decided to install STM32CubeProgrammer Winn64 to check ithe ST-LINK by trying to connect.During the installation of the tool, the installer has advised  that it is installing a driver.With no intervention, my EVB started to work, booting LINUX and all the LEDS have started flashing like a chritmasResetting the EVB, we can see Linux booting on  port COM10 115200,8,N1See the image attached when the driver work fine and how it is displayed in Win11 device manager.Have fun.Best regards,SuperGDx

Hello ST team.I am working on the boot chain from qspi NAND flash memory. The board is based on the STM32MP135F SOC and the w25n01gvzeig winbond 128MB IC. The IC is sitting on qspi bank 1 on the default BOOTROM pins (AN5474 p49).I have already succeeded the bootchain for EMMC and USB uboot successfully locates and flashes the nand with the partitions I have specified. But as set the boot pins to 111 I get 0 logs from the serial.By reading in the forum I suspect that the OTP should be programmed with the NAND layout configuration but I would like to be sure. Note the I have build tf-a with the STM32_SPI_NAND=1 on the extra flags and I get a boot log from NAND boot if i perform software reset from uboot usb.With softreset and tfa hardcoded the otp value for nand block nb[7:0]:STM32MP> resetresetting ...▒NOTICE: CPU: STM32MP135F Rev.YNOTICE: Model: STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11INFO: Reset reason (0x74):INFO: System

HelloSTM32 MP257 lists pin PC3 with additional function ADC_INP12 in ball definition table, the input source is also included reference manual ADC2 connection matrix. But it can’t be selected in STM32 CubeMX. It’s marked red in Pinout view for PC3 and not included in ADC Mode selection window. I don’t see an entry about ADC2_INP12 in errata document.  Any insights are welcomeRegardsFrank

Dear ST Support Team,I am an embedded systems engineer currently designing a custom PCB around the STM32MP257F microprocessor for a product application (a camera-based embedded system). I am using the STM32MP257F-EV1 evaluation board as our reference design for both hardware and software bring-up.We are now finalizing our own DDR memory design and are running into difficulty sourcing a DDR part that is confirmed compatible with the STM32MP257F. We understand the EV1 reference design uses two 16-Gbit DDR4 DRAMs (16-bit wide, populated for a 32-bit total bus), and that the STM32MP257 DDR controller supports DDR3L up to 2133, DDR4 up to 2400, and LPDDR4 up to 2400, in 16-bit or 32-bit configurations. However, when we check current market availability, we are not able to find DDR parts that are clearly qualified or validated against the STM32MP257F DDR controller, and we want to avoid selecting a part that causes signal integrity, timing, or DDR-training issues on our own layout.Could you

Hi ST,I am working on STM32MP257 platform and I have read some of the previous topic and thread, seems that web multimedia is somewhat supported now by using Qt at its minimalist setting. But the previous claim of “ST is working on enabling chromium/ web browser, and expected to have it out by late 2025” hasn’t really got any update.Can we know if we really have a definitive answer or status update or is there any example or demo? 

Hi! I tried to stream a 1080p (big buck Bunny) video with gstreamer. It seems that it was falling back to software and starts lagging.Are there any known issues with gstreamer for the MP2 i should be aware of? I have not used the latest OpenSTLinux version yet. I'm using v26.02.18. Still: kmscube is working perfectly in 1080p. So, I assume the the Vulkan/OpenGL ES is working properly as it should.

Hi,I am using an STM32H7S3L8 with D-Cache enabled and want to place DMA buffers in a dedicated non-cacheable SRAM region.My linker script places the DMA section in SRAM2:SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 16KSRAM_DMA (xrw) : ORIGIN = 0x30004000, LENGTH = 16K.dma_buffer (NOLOAD) :{ . = ALIGN(32); __dma_buffer_start__ = .; KEEP(*(.dma_buffer)) KEEP(*(.dma_buffer*)) . = ALIGN(32); __dma_buffer_end__ = .;} > SRAM_DMAThe DMA buffer is correctly linked at 0x30004000.I configured the MPU according to the non-cacheable DMA buffer strategy described in ST's article. The relevant configuration is: static void MPU_Config(void){ MPU_Region_InitTypeDef MPU_InitStruct = {0}; /* Disables the MPU */ HAL_MPU_Disable(); /* Disables all MPU regions */ for(uint8_t i=0; i<__MPU_REGIONCOUNT; i++) { HAL_MPU_DisableRegion(i); } /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.

The MB1854B camera on the STM32MP257FDK fails to open; clicking the camera icon on the desktop results in a white screen. Is this related to hot-plugging the camera? How can this be resolved? dmesg -w log:stm32-csi 48020000.csi: Timeout waiting for VC0 stopstm32-csi 48020000.csi: Failed to stop stream:0

I am using STM32MP235 on custom board. At some point, I wanted to update the firmware via SFU using STM32CubeProgrammer.I rebooted the board in USB mode (setting the boot mode to BOOT using the pins) and launched CubeProgrammer.TF-A-programmer-usb loaded onto the board normally, but after that, the board stopped responding via DFU.After a power reset, the board boots in DFU mode, even though the internal eMMC contains the old firmware, and the default boot mode is eMMC.As soon as TF-A is loaded onto the board, the board disappears. Nothing is written to the debug port, making it seem as if TF-A failed to boot.I tried using ROMTrace TF-A. The behavior is exactly the same, and no trace is output to the port.Pin PG4 (FAILBOOTN) is connected to a red LED. During normal boot, this LED starts blinking, and after flashing the TF-A (whether via USB or Serial), it turns solid.The documentation says that the FAILBOOTN LED blinks when the board initially boots in USB/UART mode, meaning it doesn't