STM32MP157C — PA1 won't output ETH REF_CLK even though everything in software looks correct

[pawel.poplawski]

Hi,

I'm working on a custom STM32MP157C board with a Microchip LAN8742A PHY (RMII). Originally the board uses an external 50 MHz oscillator that feeds both the PHY and the SoC's PA1 (ETH1_RMII_REF_CLK) — the classic LAN8742A "REF_CLK In Mode" setup, same as ST's reference schematic. That works fine.

I'm now trying to get rid of the external oscillator and have the SoC generate the 50 MHz REF_CLK itself instead, using RCC's CLK_ETH_PLL3Q — the setup ST documents in AN5031, Figure 45 ("RCC provides 50 MHz ETH_CLK"). For this test I desoldered the two series resistors that fed the oscillator signal in, isolated the oscillator, and bridged PA1 straight to the PHY's XTAL1/CLKIN through a wire + the same 22 Ω resistor as before. I also added st,eth-ref-clk-sel; to the ethernet node in both the kernel and U-Boot device trees, rebuilt and reflashed.

Result: PHY never comes out of reset (phy_poll_reset failed: -110), and an oscilloscope on PA1 shows absolutely nothing — not even a weak or distorted signal. For reference, I checked the now-disconnected external oscillator on its own output and it's still generating a clean 50 MHz, so I know my scope and probe are working fine — this really is nothing coming out of the SoC.

What's confusing me is that everything I can check from software says this should be working:

• The clock is enabled and at 50 MHz in the kernel's clock tree (clk_summary shows ethck_k/ck_ker_eth both at 50000000, enabled).
• The actual SYSCFG_PMCR register bit for ETH_REF_CLK_SEL (bit 17, register at 0x50020004) really does get set by the driver — I read it as 0 before Linux boots (via U-Boot) and 1 right after the failed probe (via Linux's regmap debugfs). So it's not being silently dropped somewhere.
• Pinctrl shows PA1 correctly muxed to AF11, owned by the ethernet device, configured push-pull with no pull and medium speed — nothing unusual there.
• I even double-checked it's not something in the secure world (OP-TEE/TF-A) blocking the register write, by going through our actual pinned kernel/OP-TEE/TF-A source — nothing there touches this register or gates it via SCMI/ETZPC/RIF for this SoC.
• I also tried unbinding and rebinding the driver on an already-running system (so the clock has been stable for a while, ruling out some kind of startup race) — same failure, same nothing on the scope.
• And the PCB trace itself is proven fine, since it's the exact same trace/via that used to carry the working signal into the SoC from the external oscillator.

So as far as I can tell, every register and every config layer I have access to says this should work, and physically it just doesn't. Is there something else needed to actually get PA1 driving in this mode — maybe something around IO compensation (CMPCR) for that pin's voltage domain, or some other step beyond setting st,eth-ref-clk-sel and selecting CLK_ETH_PLL3Q as the clock source? Or is "RCC as REF_CLK source" from AN5031 Fig. 45 possibly not fully working as documented on production STM32MP157C?

Thanks!