STM32MP257F Resource Isolation Framework (RIF) - Detailed Core Ownership Matrix for Cortex-A35 and Cortex-M33

[Nilay Patel]

Hello ST Team,

I am working on a design based on STM32MP257F and would like to better understand the Resource Isolation Framework (RIF) and resource ownership between the Dual Cortex-A35 and Cortex-M33 cores.

I understand that peripherals can be assigned to different processing domains, but I am looking for a detailed reference that clearly defines:

1. Which peripherals are typically operated by the Cortex-A35 and which by the Cortex-M33?
2. Is there any official resource ownership matrix available for STM32MP257F?
3. Can all GPIO banks  be assigned independently to either Cortex-A35 or Cortex-M33?
4. Are there any peripherals that are exclusively accessible by one core and cannot be reassigned?
5. How is ownership handled for the following peripherals?
   • GPIO
   • Ethernet MACs
   • USB2.0 / USB3.0
   • FDCAN
   • I2C
   • SPI / OCTOSPI
   • UART / USART
   • SDMMC
   • DDR Controller
   • GPU / VPU / NPU
   • LTDC / DSI / LVDS
   • ADC / DAC
   • Timers
   • DMA / GPDMA
6. Is there a document showing:
   • Peripheral-to-core mapping
   • Security attribution
   • Trusted/Non-Trusted domains
   • RCC ownership
   • Interrupt ownership
   • DMA access permissions

I am particularly interested in obtaining a complete isolation and ownership table showing:

• Peripheral Name
• Cortex-A35 Access
• Cortex-M33 Access
• Shared/Exclusive Resource
• Secure/Non-Secure Capability
• RIF Configuration Requirements

Could ST please point me to the relevant application note, reference manual chapter, wiki article, or provide an example project demonstrating a mixed A35/M33 system partitioning?

Thank you.

[Nilay Patel]

Hi, Is there any update regarding this query?

[Nilay Patel]

Hi, Is there any update regarding this query? We are waiting for your answer and supports

[Erwan SZYMANSKI]

Hello ​@Nilay Patel ,
I am not sure we have a big matrix summarizing all the cross configuration you can set IP by IP for the RIF firewall configuration. However please find below some inputs that can guide you:

• Wiki articles can help you to go forward on RIF understanding and configuration: https://wiki.st.com/stm32mpu/wiki/STM32MP2_firewall_configuration.
  Note that OP-TEE is responsible to configure the RIF assignments in A35-TD setup.
• You can use CubeMX as a graphic tool to configure it (as mentioned in the wiki article above).
• In the Starter Package provided by ST, you have different kind of image you can flash on your target as example:
  •  optee.tsv: also called the “open” configuration. We set as little configuration as possible for the firewall.
  • ca35tdcid-ostl-optee.tsv: present a much more precise configuration and closer to what should be a final product (adapted to our evaluation kit).
  • ca35tdcid-ostl-m33-examples-optee.tsv: this image assign more peripheral to the M33 cortex to make run a larger variety of example on it. 
• On our default distribution, we provided a debug sysfs entry to check all the firewall assignments. On your running target, you can make cat /sys/kernel/debug/stm32_firewall/rifsc to check it.

Concerning GPIO banks, yes they can be assigned to one core or another.

I would advise you to first explore the Wiki and CubeMX RIF configuration that will guide you a bit deeper on this topic.

Kind regards,
Erwan.

[Nilay Patel]

Dear ST Team,

Thank you for the information regarding the Resource Isolation Framework (RIF) on the STM32MP257F.

We understand that there may not be a single comprehensive matrix documenting every possible RIF configuration and all IP-by-IP combinations between the Cortex-A35 and Cortex-M33.

However, for our system architecture and long-term design planning, we would like to clarify one important point.

Could you please confirm whether there are any peripherals or resources on the STM32MP257F whose ownership or accessibility is hard-wired/fixed to a specific processing core or domain, and therefore cannot be reassigned through the RIF/security configuration?

In particular, we would like to understand whether any of the following resources have fixed core/domain dependencies:

• GPIO banks

• Ethernet MACs

• USB 2.0 / USB 3.0

• FDCAN

• I2C

• SPI / OCTOSPI

• UART / USART

• SDMMC

• DDR Controller

• GPU / VPU / NPU

• LTDC / DSI / LVDS

• ADC / DAC

• Timers

• DMA / GPDMA

• RCC/clock and reset control

• Interrupt controllers and interrupt routing

Our main concern is to identify any architectural restrictions that could affect future A35/M33 partitioning. For example, if a peripheral is permanently associated with the Cortex-A35 or Cortex-M33, or if a resource can only be accessed from a particular security/domain context, we would like to account for this in our hardware and software architecture now.

Could you please confirm:

1. Which resources, if any, are hard-wired to a specific core/domain?

2. Which resources can be assigned/reassigned using the RIF?

3. Whether there are any resources that can be accessed by both A35 and M33 but require specific security/non-secure or RIF configuration.

4. Whether GPIO banks can be independently assigned between the A35 and M33 domains.

5. Whether RCC, interrupt routing, DMA access, and other system-level resources have any fixed ownership restrictions.

   Even if a complete RIF ownership matrix is not available, confirmation of the fixed/hard-wired resources and the resources that are configurable through RIF would be very helpful for us to ensure that our architecture does not encounter an ownership limitation later in the development cycle.

   Thank you for your support.

[Nilay Patel]

Hi ST team,

Is there any update?