Question
STM32MP257F Resource Isolation Framework (RIF) - Detailed Core Ownership Matrix for Cortex-A35 and Cortex-M33
Hello ST Team,
I am working on a design based on STM32MP257F and would like to better understand the Resource Isolation Framework (RIF) and resource ownership between the Dual Cortex-A35 and Cortex-M33 cores.
I understand that peripherals can be assigned to different processing domains, but I am looking for a detailed reference that clearly defines:
- Which peripherals are typically operated by the Cortex-A35 and which by the Cortex-M33?
- Is there any official resource ownership matrix available for STM32MP257F?
- Can all GPIO banks be assigned independently to either Cortex-A35 or Cortex-M33?
- Are there any peripherals that are exclusively accessible by one core and cannot be reassigned?
- How is ownership handled for the following peripherals?
- GPIO
- Ethernet MACs
- USB2.0 / USB3.0
- FDCAN
- I2C
- SPI / OCTOSPI
- UART / USART
- SDMMC
- DDR Controller
- GPU / VPU / NPU
- LTDC / DSI / LVDS
- ADC / DAC
- Timers
- DMA / GPDMA
- Is there a document showing:
- Peripheral-to-core mapping
- Security attribution
- Trusted/Non-Trusted domains
- RCC ownership
- Interrupt ownership
- DMA access permissions
I am particularly interested in obtaining a complete isolation and ownership table showing:
- Peripheral Name
- Cortex-A35 Access
- Cortex-M33 Access
- Shared/Exclusive Resource
- Secure/Non-Secure Capability
- RIF Configuration Requirements
Could ST please point me to the relevant application note, reference manual chapter, wiki article, or provide an example project demonstrating a mixed A35/M33 system partitioning?
Thank you.
