STM32U585 VDD Fall Time Rate Violation and VBAT Drop During Overvoltage Failure Condition
Hello ST Team,
We are using the STM32U585 in a PCI security application and have encountered a question regarding the VDD fall-time specification during an abnormal power failure scenario.
Test Scenario
We are performing a security certification test similar to an "Operation Voltage Extreme High/Low Test".
An overvoltage is intentionally injected at the USB power input to create a system fault condition and verify:
- Secure data protection functionality
- Active Tamper functionality
- Security behavior during abnormal power events
Observed Behavior
When the input voltage reaches approximately 11V, the front-end power IC fails and VDD33 becomes effectively shorted to GND.
The measured power-down waveform shows:
- VDD33 collapsing rapidly
- VBAT also exhibiting a noticeable voltage drop
- Measured VDD fall-time rate ≈ 2.6 µs/V
According to the STM32U585 datasheet, the VDD fall-time rate specification appears to require a slower ramp-down condition.
Questions
-
What is the expected behavior of STM32U585 when the VDD fall-time rate is outside the datasheet specification?
Possible concerns include:
- Improper BOR/POR operation
- Unexpected reset behavior
- Loss of secure SRAM contents
- Impact on Tamper detection logic
- Other undefined operating states
-
Why would VBAT also drop when VDD suddenly collapses?
We would like to understand whether:
- Internal protection structures could create a temporary current path between VDD and VBAT domains.
- Backup domain circuitry may draw abnormal current during such a failure event.
- This behavior is expected under catastrophic VDD failure conditions.
-
Are there any application notes or design recommendations for handling extremely fast VDD collapse caused by external power-stage failure?
Device
- MCU: STM32U585
- Security Features Used:
- Backup Battery (VBAT)
- Active Tamper
- Secure Data Storage
Any guidance would be greatly appreciated.
Thank you.