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MikeInMinnesota
Associate II
October 22, 2026
Question

FLASH_SECEPOCHR_PRG and FLASH_NSEPOCHR_PRG Read Back as 0 After Reset / Option Byte Reload

Device: STM32H523xx

Reference Manual: RM0481

Description of Issue:
We are observing an apparent discrepancy between the documented initialization behavior of the Epoch programming registers and the actual silicon behavior.

According to RM0481 Table 90 (Option byte loading description), both FLASH_SECEPOCHR_PRG and FLASH_NSEPOCHR_PRG are specified to be loaded from option bytes during a system reset / option byte reload sequence. This implies that after a successful boot or reload cycle, the _PRG registers should mirror the current active values found in their respective _CUR registers (FLASH_SECEPOCHR_CUR and FLASH_NSEPOCHR_CUR).

However, during live register readbacks in our firmware (running at HDPL1), both FLASH_SECEPOCHR_PRG and FLASH_NSEPOCHR_PRG consistently read back as 0x00000000, even when the corresponding _CUR registers contain non-zero, successfully committed epoch values.

Per §7.11.21 and §7.11.22, both _CUR registers allow Secure/Non-Secure reads and are behaving exactly as expected. The corresponding _PRG registers do not have any specific HDPL or security masking limitations documented in the manual that would account for a read-as-zero behavior post-boot (unlike FLASH_HDPxR_PRG in §7.11.40).

Questions for Community/Engineering/FAEs:

  1. Are the FLASH_SECEPOCHR_PRG and FLASH_NSEPOCHR_PRG registers intended to be write-only / read-as-zero once the option byte reload sequence completes or once the flash interface stabilizes?
  2. If they are readable, under what specific isolation, HDPL, or system conditions will they return their true loaded value rather than 0x0?
  3. Is Table 90 incorrect regarding the initialization source for these specific _PRG registers, or is this a known documentation erratum in RM0481?
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