STM32 MCUs

Hi all, I'm planning to use USB (DFU mode) for production programming of the STM32C071K8U6 — including the very first firmware upload. The board has no external crystal; I intend to rely solely on the internal RC oscillator.   A few questions: 1) Is USB DFU feasible on this specific part without an external crystal? I've read that not all STM32 variants support USB boot without an external crystal (due to clock accuracy requirements for USB). Can anyone confirm whether the STM32C071K8U6's internal oscillator is sufficiently accurate for this?   2) Are there any specific hardware or configuration requirements I should be aware of for first-time USB DFU programming on this part? As the moment I just have the two USB traces connected to the USB connector but no 5V (VBUS) connected anywhere to the micro. I also have a pushbutton on the BOOT0 pin.   3) What USB speed does the built-in bootloader use, and is it possible to force a lower speed? The reason I ask is that the USB

https://www.linkedin.com/posts/edwin-amaya-63006b225_next-little-free-project-is-a-segger-rtt-activity-7459971377140469760-ik6Vhttps://github.com/EdwinFairchild/ProbeStream 

Hi, I am currently implementing an HTTPS server using mbedTLS 3.6.5 and LwIP on an STM32H7S7L8 platform running FreeRTOS.Our mbedTLS configuration  are fully functional, as we already have a stable, working TLS implementation on an MQTT client using the same stack.However, we are encountering an issue during the TLS Handshake phase on the server side after configuring the client sockets to non-blocking mode (O_NONBLOCK). While the listening socket correctly accepts incoming connections, the handshake loop fails.I have attached the relevant snippet of our server thread implementation, including our I/O callbacks.Could you please review our non-blocking I/O logic and handshake loop to see if we missed a specific configuration requirement or state handling for mbedTLS 3.x in server mode?  /* STM32CubeMX Specific Parameters (not defined in opt.h) ---------------------*/ /* Parameters set in STM32CubeMX LwIP Configuration GUI -*/ /*----- WITH_RTOS enabled (Since FREERTOS

Hi, we have purchased stm32h750vbt6 microcontroller for analog signal validation with 10k potentiometers to integrate with game controller joystick especially joy.cpl using windows 10 OS.   We have dealt with DMA Circular mode configuration pointing cortex-M7 DRAM to 0x30000000 to retrieve the analog signals associated with respective 10k potentiometers. Totally we have four analog pins such as PA0,PC0,PA3 and PC5 from ADC1 & ADC2 with proper distinguished rank allocation alongside desired maximum sampling cycles but although we have altered and tested with different values of this above configuration it ended up with ADC channel leakage which is declared 16 bit ADC.    Moreover we have tried adding external 100nf capacitors to avoid these linkage but failed.    We kindly request you to resolve the ADC channel leakage in our current stm32 Project. Our entire stm32 project attached for your reference and fault identification.  

I am using the Analog Devices EVAL-ADE9430 Evaluation board for testing one of their devices. The Evaluation board uses the NUCLEO-144 STM32F413ZH processor. I am using the Keil uVision development setup to run and debug code.  I am specifically concentrating on the SPI Bus Driver and the timing. I have no previous experience with STM Devices and how the SPI transfers happen in the processor. so I apologize a head of time.  My question is very basic I am trying to understand how the NUCLEO-144 STM32F413ZH board is transmitting the data over the SPI Bus. What setup is involved and what kicks off the actual transmission in the the HAL_SPI_Transmit() code below. The code i am using is transmitting 8 bits at a time.  The Chip Enable (SS) is set active prior to this code. I see a structure called hspi that has a bunch of parameters that are initialized at line 29 below By single stepping know when line 108 below executes I can see 8 bits of data on my scope. I

DeviceSTM32H563ZIT6, single binary (no separate bootloader), dual-bank OTASetup Bank1: Current running firmware (original)Bank2: New OTA firmware (potentially corrupted)IWDG: Started in Bank1 before swapOTABootSafetyCheck: In Reset_Handler of every binary buildBKP0R: Boot counter set before swapProblemAfter bank swap, if Bank2 firmware is corrupted and Reset_Handler never executes:  Bank swap → resetCPU reads 0x08000000 → SP (may be valid)CPU reads 0x08000004 → Reset vector (may be valid)CPU jumps to Reset_Handler addressReset_Handler code is corrupted → garbage instructions → crashOTABootSafetyCheck never runsBoot counter never incrementsIWDG fires → reset → same crash → infinite loopRollback never happensBank1 original firmware never recoversDevice is permanently stuck What We Have Tried1. OTABootSafetyCheck in Reset_Handler  asmReset_Handler: ldr r0, =_estack mov sp, r0 bl OTABootSafetyCheck ; before SystemInit and main bl SystemInit bl __libc_init_array bl

Hello, I am working on a project using DMA and UART HD to communicate between multiple MCUs.  I have an issue where when one MCU starts up, it momentarily interrupts the UART HD bus and sometimes causes a UART and/or DMA error.Since I am using the STM32CubeMX packages for the HAL libraries, I tried to recover from the issue by several means, but I noticed there seems to be no provided method in the stm32h5xx_hal to recover once hdmarx->State = HAL_DMA_STATE_ERROR.  Calling any of the UART or DMA abort functions (HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_DMAStop()) does not reset the DMA State.  The call chain for HAL_UART_Receive_DMA() eventually checks the DMA State and just returns an error.I have found 2 methods that manage to work around the issue, but I am not satisfied with them because they are not at all elegant:Method 1: Call HAL_DMA_DeInit(), reset the Parent pointer back to huart, then call HAL_DMA_Init().  I feel like it might be missin

I'm looking for a working example of how to program the OTP memory on the STM32H573.I am looking to program with TrustZone enabled, from secure mode.  I'm using STM32Cube_FW_H5_v1.4.0, and am not in a good position to move to v1.5.0.  Any working example would do, using HAL, LL or direct register access.Thanks in advance.-Rob

Hello all, I've been having trouble with the ADC system on the STM32G071G8U6.  I'm using the STM32CubeMX to generate initialization code.  I have 5 external A/D inputs and it appears I am not getting readings anywhere near the real values, so I have switched to trying to just read the internal reference.  I hope that if I can get the internal reference or the temperature to read correctly, I'll be able to solve the problems with the external inputs. My VDD is provided from a 2.5 volt LDO.  Looking at it with a DVOM, that looks accurate. I am running the A/D at 12 bit resolution and my clcok prescaler is Synchronous clock mode divided by 2.  I have the sampling time set to the maximum available in Cube, 160.5 cycles. I have a polling routine running every 1 second that reads all 5 external and all 3 internal channels. I set the VREFEN and TSEN bits in the ADC CCR register at the end of init and leave them enabled. I realize there may be board related problems wi

Hello,I am designing a high-speed data logging architecture using STM32H743VIHx. I would like the community to validate my DMA architecture and answer specific questions about eMMC access. I did not find answers in the forum and I am also not an expert in microcontroller hardware/software architecture. --- SYSTEM OVERVIEW ---The logging produces a continuous signal sampled by the ADC. I need to log raw data samples along with GPS and IMU data to an eMMC for post-processing.Key parameters:- ADC: 14-bit dual interleaved on PA6 (ADC12_INP3), differential ~10 MSPS effective- eMMC: S32 GB, eMMC 5.1- SDMMC1 in 8-bit MMC mode- IMU: on SPI2 (PB12-15) at 8 kHz- GPS: on UART4 at 115200 baud --- PROPOSED DMA ARCHITECTURE ---Four concurrent DMA paths:1. ADC1+ADC2 interleaved → DMA1_Stream0 → AXI SRAM (ping buffer)Triggered by ADC1 EOC, reads CDR register (32-bit = 2 interleaved samples)Rate: ~20 MB/sPriority: VERY HIGH2. AXI SRAM (pong buffer) → MDMA_Channel0 → SDMMC1 → eMMCTriggered aft

ST moderator: updated the title to be more concise according to the below exchanges. Hello All,   I am facing a problem for debugging one of the board which uses stm32h7 controller. I am not sure why this is happening but on other board I am able to debug it, but for first one its not working. Though the code and debug config settings are same for both the board and using same system to debug both, but on one board I am able to debug while on other its is not. so could you please tell me what I can try to resolve this issue.   Thanks, SD 

  Hello ST Community,I am working on STM32H7B3LIH6Q with TouchGFX.I have successfully initialized the TFT RGB display on hardware, and the RGB test output is working properly. I created two screens in TouchGFX Designer, where pressing a touch button on Screen 1 should open Screen 2.This works correctly in the PC simulator, but on actual hardware the touch command/button press is not working. The display is visible, but touch input is not detected.I have attached the hardware output image and my touch enable/source code for reference.Could anyone please suggest what I should check in the hardware touch interface? Is the issue likely related to , BSP touch driver, I2C touch controller initialization, or touch coordinate mapping?Thank you,Vijaya.  

Hi, I have all configured using internal loop FDCAN1 and there is not working on my STM32G474RE-Nucleo board 

Hi, We are busy making a setup with 2 nucleo-c092rc boards. Our first test was to send from board 1 to board 2 by the integrated CAN interface on these boards. We started at 1Mbits and this worked great. Also on 4Mbits the setup worked great. But we also want to test this on 8Mbits and now the transmitter is not sending correctly. We only see that the arbitration phase is send out and a couple of bits of the data part, but then the transmitters stops sending. We have tried with internal HSI(48Mhz) and external HSE crystal which is also 48Mhz on the nucleo boards.  We calculated the values for the SyncJumpWidth and timeseg1 and 2 and also tested with values slightly altered. hfdcan1.Init.DataPrescaler = 1; hfdcan1.Init.DataSyncJumpWidth = 2; hfdcan1.Init.DataTimeSeg1 = 2; hfdcan1.Init.DataTimeSeg2 = 3; But we allways have the same outcome. Sometimes it's not sending anything and sometimes only a small part of the total message of 64 bytes. What could be the issue here?  

This is some feedback for the STM32C5 OEMiRoT example provided by ST.This is based on the STM32C5-MCU-HAL2.0.0 pack download 06-05-2026.Attached you can also find the CMake Config files for the example, specifically for the NUCLEO-C542RC board.General Bug Provisioning Python ScriptThe provisioning python script has a small bug when it comes to the prebuild script which adjusts the linker files.These files are compiler specific so the correct adjustment function needs to be called.This compiler dependent code is missing in the `_update_linker_define()` function in `STM32C5-MCU-HAL/rot/rot_provisioning/helper/project/project_generic.py` starting at line 318:linker_path = self.config.get_compiler_linker(compiler) value = f"0x{self.flash_layout.get_flash_layout(define):X}" update_define_in_file(linker_path, define, value)change tolinker_path = self.config.get_compiler_linker(compiler) value = f"0x{self.flash_layout.get_flash_layout(define):X}" if (compiler == "gcc"): update_variable_

Hello, ST expert For GPIO structure, what are the differences between FT and TT mode? Are there any differences for the ESD diode and the other diode in these two modes?     BR Yang  

I am working on UART communication between an STM32H563 and a Raspberry Pi CM4.Currently, I am using UART without hardware flow control (RTS/CTS disabled). During continuous communication, I am frequently getting ORE (Overrun Error) on the STM32 side.Configuration details:MCU: STM32H563Communication: UARTFlow control: DisabledUART mode: InterruptPeer device: Raspberry PiI would like to know:1. What is the best workaround to avoid ORE errors without enabling hardware flow control?2. Is it reliable to use UART communication continuously without RTS/CTS?3. What are the recommended UART settings or software handling methods for STM32H5 series?4. How should ORE recovery be handled properly in STM32H563?Currently, once ORE occurs, The data became lost.

Hi All,I've just been watching an ST tutorial video on how to implement  bare-metal Device CDC USB  on an STM32U3.During the video, the lecturer says that the code is available within the workshop download. No link is provided to the workshop code....Does anyone know where I can find it? This is the video in question : https://youtu.be/m8ph9JIY5QE?list=PLTJzs51NlEIAHFfePhKJPsnWvT5XidJuU&t=1164Any help would be appreciated.CheersMichael 

Hello ,I am working on a project with the STM32L562CET6 microcontroller and have encountered an issue with the timer interrupt callback function.   1. I configured TIM6 as the clock source for the microcontroller. Consequently, the HAL_TIM_PeriodElapsedCallback() function is automatically triggered whenever the TIM6 interrupt occurs.   2. Now, I have configured TIM2 for a different purpose, but I noticed that when the TIM2 interrupt occurs, the same HAL_TIM_PeriodElapsedCallback() is triggered.Since the HAL_TIM_PeriodElapsedCallback() is defined with the weak attribute, I understand that I can redefine it in my user code. However, this causes conflicts when multiple timers (like TIM6 and TIM2) trigger this callback.Questions:  1. Is there a way to alias or redirect the HAL_TIM_PeriodElapsedCallback() to separate functions for different timers (e.g., one for TIM6 and another for TIM2)?  2. Is there any other specific callback function available for timers i

Hi All,    I want to do something very basic, but somehow cannot manage to do it. What happens if you have a PWM signal on an IO Pin, generated by a timer, and you disable the timer?  What happens to the physical IO Pin ? Is it stuck at the state where it was when you disabled it ?, Does it go Low ? Or High. The Idle state of the Timer is Low, and the On state High.    Thanks,  DJ 

Hello ST Community team,I would like to report a possible inconsistency in the STM32 MCU Portfolio Selector regarding Ethernet filtering for the STM32C5 series.While selecting MCUs using the Portfolio Selector, I filtered devices through:- EthernetThe reference STM32C593CET6 appears as supporting Ethernet functionality. However, according to DS15136 (Table 1), this specific MCU does not include the Ethernet peripheral.This may create confusion for developers, especially since the STM32C5 family is still relatively new and many users rely on the Portfolio Selector during early device selection.Could you please review and correct this behavior.Ps: more details available on this post. Best Regards.II

Hello everyone,I am currently working with the Aliro software expansion for STM32Cube using the new STEVAL-ALOCKCB board (Aliro access control reference design based on STM32WBA65RI, ST25R300, and STSAFE-A120).Both the hardware and software are in their original, unmodified state from ST. The nfc12ble project builds successfully without any issues.However, I am encountering a consistent problem:the function CryptoInit() always returns false.From debugging, I can see that the failure originates from the CheckReaderPubK() function, which internally calls isValidProvisioning(). This function also returns false, causing the entire initialization to fail.It seems that the provisioning structure is not considered valid. In particular:The check prov->isValid == DEVICE_PROVISIONING_STRUCT_IS_VALID fails.DEVICE_PROVISIONING_STRUCT_IS_VALID is defined as 0xA5A55A5A (decimal: 2779077210).However, the actual value read from flash appears to be different (e.g., 0xFFFFFFFF), which suggests that t

Dear STMicroelectronics Community / Support Team,I hope you are doing well.I am currently working with the STM32N6 Discovery Kit and noticed that it uses an external Octal NOR flash device with the part number MX66UW1G45G. However, I have been unable to locate a public datasheet for this exact component.I was able to find datasheets for similar parts such as MX66U1G45G and MX66UM1G45G, but not for the “UW” variant used on the board. This has led to some confusion regarding the exact specifications, supported features, and command set of the device.I would appreciate your guidance on the following points:Is MX66UW1G45G a custom or internal part number used specifically for STM32 evaluation boards?Is there a publicly available datasheet for this device, or can it be shared upon request?Can MX66UM1G45G (or another publicly documented part) be considered a fully compatible equivalent for development purposes?Are there any specific differences (e.g., command set, timing, interface behavior)

Hello, I am working on an SNMP implementation using STM32H753ZI with the LwIP Ethernet stack. Currently, SNMP v1 is working successfully, including trap generation and reception testing using Net-SNMP tools. I am able to send enterprise-specific traps from the STM32 device. Below is the trap code currently working for SNMP v1: void send_temp_fault_trap(void) { static const u32_t enterprise_oid_arr[] = {1,3,6,1,4,1,50598}; struct snmp_obj_id enterprise_oid; enterprise_oid.len = LWIP_ARRAYSIZE(enterprise_oid_arr); memcpy(enterprise_oid.id,enterprise_oid_arr,sizeof(enterprise_oid_arr)); ip_addr_t dst; IP4_ADDR(&dst, 192,168,0,255); snmp_trap_dst_ip_set(0, &dst); snmp_trap_dst_enable(0, 1); static const u32_t msg_oid_arr[] = { 1,3,6,1,4,1,50898,10 }; static struct snmp_varbind vb; static struct snmp_obj_id msg_oid; static char msg[] = "System Working"; msg_oid.len = LWIP_ARRAYSIZE(msg_oid_arr); memcpy(msg_oid.id,msg_oid_arr,sizeof(msg_oid_arr)); vb.next = NULL

Hello everyone,I have encountered a strange issue with my UART transmission function on an STM32 microcontroller operating in Half-Duplex Open-Drain mode.Currently, the function works perfectly fine without checking the TC flag. However, when I add a check to wait for the transmission completion at the end of the function, my logic analyzer shows completely garbled bytes (corrupted data).Here is the code that works perfectly (without the TC check):void send_array(uint8_t *arr, uint8_t size) { /* Receiver disable */ USART3->CR1 &= ~(CR1_RE); for (int i = 0; i < size; i++) { /* Wait until Transmit data register is empty */ while(!(USART3->SR & SR_TXE)){} /* Send byte */ USART3->DR = arr[i]; } /* Receiver enable */ USART3->CR1 |= CR1_RE; }And here is the modification that breaks the transmission and leads to garbled bytes on the analyzer:void send_array(uint8_t *arr, uint8_t size) { /* Receiver disable */ USART3->CR1 &= ~(CR1_RE); for (int i