STM32 MCUs

Hi,we have a question regarding the Secure Manager Internal Trusted Storage size on the STM32H73 series.We have configured the following options:external flash profile 0 secure modules (=SMAK_0 ?)According to UM3254 it is our understanding the ITS size can now be up to 56 Kbyte:Our application project.py prebuild seems to extract value “9”, which means 9 * 8 Kbyte (Flash sector size) = 72 Kbyte? Jul  8 13:27:10 2026 : [INF] Searching the parameter with <Name>ITS size</Name> element2026-07-08 13:27:10,542 - DEBUG - Wed Jul  8 13:27:10 2026 : [INF] Parameter found. Verifying information of '<Value>0x9</Value>'2026-07-08 13:27:10,543 - DEBUG - Wed Jul  8 13:27:10 2026 : [INF] The modification is not necessary2026-07-08 13:27:10,543 - DEBUG - Wed Jul  8 13:27:10 2026 : [INF] The tag <Value> has already the correct content (0x9) Is there a misunderstanding on our end about the profile, memory configuration, UM3254 table, the prebuild proccess or the conversion

Hi everyone,I am new to the MCSDK environment and currently working on a porting project from MCSDK 5.4.8 to 6.4.1. I have been stuck on this for weeks and I am honestly getting desperate as I cannot find a way forward.I need a functional routine to handle encoder alignment that is compatible with the 6.4.1 framework. The alignment must be performed solely upon user request, and it is critical that the motor does not start running after the alignment sequence. I am looking for a direct replacement for the legacy MCAlignEncoderMotor1() API.I have already attempted the implementation suggested in this thread: MCSDK 6.3 - Correct way to restart / retrigger encoder alignmentUnfortunately, this solution does not work for my setup. Could you please provide guidance on how to trigger this alignment in isolation within the 6.4.1 architecture?Best regards,bolla_bo

Hello,I am working on a design incorporating the STM32U3C5CIU6Q in SMPS mode. This package includes two VDD11 pins. I am having trouble interpreting the datasheet when it comes to the number of inductors I will need. This note under Figure 24 in the datasheet is clear that each pin will need a capacitor to VSSSMPS, but it seems like it could also imply that each VDD11 pin requires its own inductor between VLXSMPS.The power supply scheme (with SMPS) is also not clear to me: This section seems more like it is expecting a single inductor:Am I okay to use a single inductor between the VLXSMPS pin and VD11 node, with each VD11 pin having its own capacitors, or should I treat each VD11 as a separate loop with its own inductor as well?Thanks for any help!

NUCLEOWB55RG I set I2C3 in MX. I have 2 x temp sensors & 2 x accelerometers in the bus./* Snippets of code to show how I2C3 is set up & used */#include "main.h"#include "adt7410.h"#include "adxl345.h"I2C_HandleTypeDef hi2c3;ADT7410 temp_0;ADT7410 temp_1;ADXL345 acc_0;ADXL345 acc_1;static void MX_GPIO_Init(void);static void MX_I2C3_Init(void);int main(void){ HAL_Init(); MX_GPIO_Init(); MX_I2C3_Init(); /* ADT7410 set up */ /* temp_0 at 0x48 * temp_1 at 0x49 */ temp_0.adti2c = &hi2c3; // I2C Handler ADT7410_Init(&temp_0, 0x48); // I2C address depends of A0 and A1 pins ADT7410_Reset(&temp_0); // Optional ADT7410_SetResolution(&temp_0, ADT7410_16BITS); // Put the device in 16 bits resolution temp_1.adti2c = &hi2c3; // I2C Handler ADT7410_Init(&temp_1, 0x49); // I2C address depends of A0 and A1 pins ADT7410_Reset(&temp_1); // Optional ADT7410_SetResolution(&temp_1, ADT7410_16BITS); // Put the

Firmware Package: STM32Cube_FW_H5_V1.6.0 Product ProblemDA regression fails with timeout. I cannot recover the board. I was trying to run the STiROT Template example (STiROT_Appli) on the STM32H573I-DK board. 1. I ran a custom provisioning script (based on ob_flash_programming.sh + obkey_provisioning.sh)2. During image flashing step, I accidentally flashed an unsigned binary (appli.bin) instead of the signed image (appli_init_sign.hex)3. OBKey provisioning (DA_Config.obk, STiRoT_Config.obk, STiRoT_Data.obk) may have failed due to the MCU being in an unstable state4. I then set Product State to PROVISIONED (0x2E) Discovery output Discovery succeeds and shows- PSA lifecycle: ST_LIFECYCLE_IROT_PROVISIONED - ST provisioning integrity status: 0xf5f5f5f5 - ST HDPL1 status: 0x1 - Permission: Full Regression is listed as available Regression attempt Using default keys from the firmware package (not regenerated): - Key: DA/Keys/key_3_leaf.pem - Certificate: DA/Certifica

In RM0481 rev 4 April 2025 I find the following text:7.6.8 Write protectionA write-protected group of sectors cannot be erased nor programmed. As a result, a bankerase cannot be performed if one group of sectors is write-protected, unless a NVSTATEtransition to OPEN is triggered (erasing the whole user flash memory). It is not clear what NVSTATE is in this context. Is this a left-over from documentation of a different MCU? I don’t think it is PRODUCT_STATE. Because to my understanding you can have a PRODUCT_STATE > OPEN and not enable TrustZone and then write to FLASH_WRP1R_PRG to turn off write protection - you should be able to do a bank erase on bank 1. You can set initial values with an OB but I can’t see any documentation that this also makes changing FLASH_WRP1R_PRG illegal and the relevant OBs are not protected by PRODUCT_STATE the same way as e.g. SECWM and HDP.Same reasoning for flash bank 2.And if you enable TrustZone, it is stated that FLASH_WRP[1, 2]R_PRG is non-secure.

Hello ST Community,I am evaluating the security features of the STM32H733 (Cortex-M7) for a project that uses:A custom bootloader stored in internal flash The main application stored and executed from external QSPI/Octo-SPI flashI have the following questions regarding Secure Firmware Install (SFI):Is SFI for internal flash officially supported on the STM32H733? (I saw it was added in AN4992 Rev 8, but I would like official confirmation.) Is SFI for external flash (SFIx) supported on the STM32H733? Specifically, can the secure bootloader (RSS) decrypt and program the external application image securely during manufacturing, or is only the "host-side encryption + internal firmware configures OTFDEC" method available? If external SFIx is not supported, what is the recommended secure manufacturing flow for a design with main code in external flash?

Hi.I’m working on a custom board with a C551VET6 and trained on a NUCLEO_C562RE with ADC. I attempted the conversion in polling mode in several ways (mode=single + discountinuous=disabled  /  mode=continuous + discountinuous=3ranks) by varying the implementation of the FOR loop (including or excluding the calls to HAL_ADC_REG_StartConv and HAL_ADC_REG_PollForConv according to the selected mode); no matter what I did, as soon as I needed to convert 3 or more channels, only the first two showed distinct values, while all the other channels in the sequencer returned a value identical to that of the second channel.I found no example using more than 2 channels in a basic regular sequencer. Have you tried it at ST ?By the way, I’m working with a CTN temperature sensor and two HDC3120 giving both temperature and humidity, thus 5 channels in my case.Do I need to lower the resolution or something when the number of channel increases ?I’m not familiar with ST community mechanisms, shall I open a

Hi,I am trying to connect SDRAM AS4C16M16SB from Alliance Memmory to STM32N655X0 MCU, but i did not find any reccomended connection. I am “pinned” this memorry to MCU according STM32Cube MX software and MCU datasheet. But there is not much more information about “autoprecharge” function. Only in reference manual RM0486 is small note “The AutoPrecharge is not supported. However, FMC_A[10] must be connected to SDRAM A[0]”. But the memmory has dual function on the address 10 pin (address 10 + AP). Do you have some recommendation how this memmory connect to STM32N655X0 MCU, or is it suitable for this MCU?Below is my wiring diagram, in purple are FMC signals corresponding with pins on MCU. Is it right or am I must somehow reroute the address signal signal (A10)?Thanks a lot. R. 

Hi, Is there mistake between reference manual RM0486 and RM0090 in section SDRAM adress mapping?Where in RM0486 is: "When interfacing with a 16-bit memory, the FMC internally uses the ADDR[11:1] internal address lines to generate the external address. When interfacing with a 32-bit memory, the FMC internally usesADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to beconnected to the SDRAM A[0].The AutoPrecharge is not supported. However, FMC_A[10] must be connected to SDRAM A[0]"In RM0090 is: "When interfacing with a 16-bit memory, the FMC internally uses the HADDR[11:1] internal AHB addresslines to generate the external address. When interfacing with a 32-bit memory, the FMC internally usesHADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to beconnected to the external memory address A[0]. The AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address A[10] but it is alwa

Hi,I'm integrating an STSAFE-A110 with stsafe-a-openssl-engine V2.0.0 on a Linux/aarch64 host (Jetson AGX Orin, Ubuntu 22.04, OpenSSL 3.0.2), communicating over I2C. I've resolved a number of earlier issues (wrong I2C bus, OpenSSL 3.0 API migration, host key pairing) and now have Host Key programming, Local Envelope key generation, Product Data query, Life Cycle State query, and Command Authorization Configuration query all succeeding against the physical chip.Current issue: StSafeA_WrapLocalEnvelope and StSafeA_UnwrapLocalEnvelope behave asymmetrically.My chip's Command Authorization Configuration reports:Command 0x0E (Wrap Local Envelope): CommandAC = 0x03 (MAC), HostEncryptionFlags = 0x02 (command encryption) Command 0x0F (Unwrap Local Envelope): CommandAC = 0x03 (MAC), HostEncryptionFlags = 0x01 (response encryption)Calling Wrap with STSAFEA_MAC_HOST_CMAC, STSAFEA_ENCRYPTION_COMMAND succeeds and returns a plausible 488-byte wrapped envelope.Calling Unwrap on that same output with S

A customer asked for the process technology or process node in nano meters (nm) for the STM32F303CCT7 we use. I can not find any information on ST website. The “Sidekick” told me there is no information about. Can someone help me?

Hello,I am using the Nucleo STM32H533RE board for booting with the two stage boot path for which I am using the ST template code and referring the following   https://wiki.st.com/stm32mcu/wiki/Security:OEMiRoT_OEMuRoT_for_STM32H7S . I am able to run the provisioning script successfully but when I am connecting the serial terminal to verify the serial data sent out by the board, I am getting an error saying “[ERR] read:Wrong OBK HDPL2 cfg” as seen in below image:I tried with the following things:Regenerating the OEMuROT OBK files manually using stm32 trusted package creator Running the regression script to erase the flash and again running the provisioning script Verified if the key file names matches the script referencesCan someone help me with this issue.Let me know if any other details are required. Thanks,Amruta

Hello,I am working with an STM32N6570-DK board and facing an issue while setting up the SD card. I created a project using TouchGFX Designer, generated the code, and opened the .ioc file. In there, I enabled SDMMC2 with 4-bit Wide mode and enabled global interrupt:After checking the schematics, I noticed that the CK pin was incorrect, so I assigned the correct pin (PC2:(I made the following additional configurations:Changed all SDMMC2 pins to pull-up and set Max output speed to Very HighEnabled PWR_SD_EN (PQ7) as output level high with context FreeChanged clock from HCLK to IC4 (should not affect anything)Enabled SD_DETECT (PN12) to detect when the SD card is inserted or removedEnabled EXTI Line4 and EXTI Line12 for interruptsEnabled FileX with mostly default settings, except for increased memory and FX driver initialization:After this setup, I attempted to initialize the SD card with the following call:fx_media_open(&sdio_disk, "SDIO_DISK", fx_stm32_sd_driver, NULL, fx_sd_media_me

Have any User Guide to setup matter in STM32WBA65RI? Matter 1.5.0 is supported in STM32WBA65RI?

Hi,I am using the STM32N657-DK and running the NetX Duo WebServer example provided by STM32Cube. The application works correctly when the Ethernet link is negotiated at 100 Mbps and 1 Gbps. However, when the link speed is 10 Mbps, the web server is not reachable and communication fails.SetupBoard: STM32N657-DK Software: STM32CubeIDE / STM32Cube firmware NetX Duo WebServer example PHY: (RTL8211F-CG, if applicable) Interface: RGMIIObservations1 Gbps: Works correctly. 100 Mbps: Works correctly. 10 Mbps: Link appears to come up, but the web server cannot be accessed and network communication fails.QuestionsDoes the STM32N657-DK NetX Duo Ethernet driver fully support operation at 10 Mbps? Is there any additional MAC or PHY configuration required when the negotiated speed is 10 Mbps? Are there any known limitations or issues with the NetX Duo Ethernet driver or HAL Ethernet driver when operating at 10 Mbps? Has anyone successfully run the NetX Duo WebServer example at 10 Mbps on the STM32N65

I would like to confirm whether the Ethernet MAC available in the STM32N655x0H3Q supports 1000 Mbps (Gigabit Ethernet) operation.

Cannot wake from Stop mode using LPTIM1Board: STM32N6570-DK (STM32N657X0, Cortex-M55)RTOS: Zephyr 4.4.0Goal: Enter Stop mode and wake periodically via LPTIM1 auto-reload interrupt (~200ms)What works:Sleep mode (WFI without SLEEPDEEP) — enters and wakes correctly from GPIO EXTI and LPTIMLPTIM1 initialization — confirmed running, ISR fires (verified via counter incrementing in HAL_LPTIM_AutoReloadMatchCallback)LPTIM1 EXTI line 52 enabled — EXTI->IMR2 |= EXTI_IMR2_IM52 via __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()NVIC LPTIM1_IRQn enabled — interrupt registered and working in normal (non-Stop) operationClock restore after Stop — SystemClock_Restore() re-enables HSE, PLLs (PLL1/2/3), IC muxes back to 800 MHzWhat does NOT work:Stop mode entry → CPU never wakes. After HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI), the MCU halts permanently. No interrupt wakes it.LPTIM1 configuration:__HAL_RCC_LPTIM1_CLK_ENABLE();// Clock: LSI (~32 kHz)RCC_PeriphCLKInitTypeDef pclk = {0};pclk.Per

Hi ST community,We are evaluating motor-control architecture for a 3-phase BLDC/PMSM ESC project based on STM32G431 / STSPIN32G4.Currently we understand that STM32 MCSDK supports both:- FOC control projects- 6-step / trapezoidal control projectsHowever, we would like to clarify whether MCSDK officially supports runtime switch-over from 6-step control to FOC control in the same firmware project.Our target concept is:1. Start the motor with 6-step control or open-loop 6-step startup.2. After the motor reaches a sufficient speed / stable rotor position estimation, switch to FOC control.3. Continue running with FOC current loop and SVPWM.Questions:1. Does MCSDK officially support runtime switch-over from 6-step control to FOC control in one generated project?2. If not officially supported, is there any ST reference implementation, application note, or recommended method for implementing this handover?3. Can MCSDK-generated 6-step and FOC control modules coexist in one runtime while sharing

I started with the MC workbench and installed X-Cube-MCSDK Version 6.4.2. After installation the MC Workbench is opened, but the dialog is complete empty (except the caption). The behaviour is the same if i start the workbench via the desktop icon or as administrator.

Are there any Dual Core LoRaWAN Application examples for the STM32WL55CC that use the STM32Cube FW WL V1.5.0 (LBM) libraries?  If  there aren’t, will this be supported in the future? Thanks,Nick

I have made a bootloader for STM32F4 with dual bank and single bank structure. I have done so rudimentary testing with it and written test logs in a md file. Here is the link:-https://github.com/Tank4676/stm32-dualslot_bootloader

Hi, I use STM32H7 with STCUBE 11.1.I use RNDIS module  usbd_cdc_rndis.h to communicate with a PC.Sometimes when the PC sends a frame the STM32 replies with NAK, here is the sequence that repeats:SYNCPID OUTAddressCRCEOPSYNCPID DATA0data 30 bytesCRCEOPSYNCPID NAKEOPWhat might be the issue? Can I change the USB interval (CDC_RNDIS_FS_BINTERVAL)?BRJonas

what maximum current the DAC_output / ADC_input pin can hold if shorted to the ground. with internal buffer Off/On? STM32H753zi.

 Dear STMicroelectronics Support,In our application, the STM32H7B3I-DK board is used in a "shield" configuration: it is mounted on a carrier/daughter board(PHOTO 2) (via the Arduino connectors CN19/CN20/CN10/CN11) which supplies its power. The daughter board therefore injects a 5V voltage directly onto CN19, pin 1 (5V_VIN), without going through a USB supply or through the standard VIN input of the kit.Power configuration5 V is applied to CN19, pin 1 (5V_VIN). JP1 is configured in the 5V_VIN position. VIN (CN19, pin 8) is left unconnected.MeasurementsVoltage before R114 (1 kΩ): 5.0 V Voltage after R114: 1.6 VThis corresponds to a voltage drop of approximately 3.4 V across R114, which indicates a current of about 3.4 mA flowing through the resistor.I would like to better understand whether this behavior is expected and the purpose of R114 in this circuit.Could you please clarify the following points?Is this voltage drop across R114 normal when powering the board through 5V_VIN? What is